Fujitsu Corporation

Shuntaro Fujioka

Masahiro Yanagida

Hidenobu Ohta

Hideaki Nabekura

Shinichi Moriwaki

A pipeline operation method and a pipeline operation device in which an operation result of an operation unit can be effectively written to a register. In the pipeline operation method and the pipeline operation device, a pipeline operation unit that can perform a pipeline operation, a non-pipeline operation unit that cannot perform a pipeline operation, and a register that is shared by the pipeline operation unit and the non-pipeline operation unit are arranged. To perform an operation while an operation result of each of the pipeline units is being written into the register, translating an instruction to the pipeline operation unit is interlocked when the writing of the operation result of the pipeline operation unit overlaps with the writing of the operation result of the non-pipeline operation unit. The pipeline operation method and the pipeline operation device are applicable to a computing system where plural operation units including pipeline operation units and non-pipeline operation units share one writing port to perform an arithmetic operation.

Pipeline operation method and pipeline operation device to interlock the translation of instructions based on the operation of a non-pipeline operation unit

Asynchronous computation commands sent from a command control are held in a command queue. The executable command is selected and supplied to a pipelined asynchronous computing unit. A status area is assured for each command held in the command queue and pipeline bits indicative of a progressing state of the execution of the command in the asynchronous computing unit are stored. A queue verifier discriminates the pipeline bits and verifies that a plurality of pipeline stages does not exist in the status area of the same command and that a plurality of pipeline stages does not exist among the commands, thereby guaranteeing the correct order and operation of the execution of the commands.

Apparatus and method for verifying the order and operation of a data

A computer system includes a central processing unit, a computer maintenance unit and an input/output processing section having a plurality of input/output processing units each of which is associated with a respective input/output device. When a failure occurs in an input/output processing unit, the input/output processing unit control section detects the occurrence of a failure, reports it to the central processing unit and requests the computer maintenance unit to acquire failure information from a failed input/output processing unit and to initialize the input/output processing unit. After acquisition of the failure information, the computer maintenance unit initializes the failed input/output processing unit and reports the termination of the initialization to the input/output processing unit control section. Afterward, the input/output processing unit control section informs the central processing unit of the termination of the initialization of the failed input/output processing unit.

Growing community of inventors

Kawasaki, Japan

Shuntaro Fujioka