Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi, Ltd.

Shunsuke Toyoshima

Kazuo Tanaka

Takahiro Hayashi

Naozumi Morino

Kazuo Sakamoto

Takeo Toba

Yusuke Kanno

Masaru Iwabuchi

Toshiro Takahashi

Yasuhiro Fujimura

Yusuko Kanno

The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Semiconductor device

Semiconductor device with output circuit and pad arrangements

Semiconductor devices with output circuit and pad

Semiconductor device with output circuit and pad

Semiconductor device with output circuit arrangement

To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Semiconductor integrated circuit device

A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

Semicondutor integrated circuit device

Semiconductor integrated circuit device having I/O circuitry for low voltage operation

The present invention provides a semiconductor integrated circuit having two kinds of input/output circuits realizing higher speed and higher packing density with rational configuration. The semiconductor integrated circuit has a first input/output circuit operating on a first power source voltage, an internal circuit operating on a second power source voltage lower than the first power source voltage, and a second input/output circuit operating on a third power source voltage lower than the first power source voltage. In an output circuit of the first input/output circuit, signal amplitude corresponding to the second power source voltage is converted to signal amplitude corresponding to the first power source voltage by a level shifter, and a P-channel MOSFET and an N-channel MOSFET constructing the output circuit are driven. In an output circuit of the second input/output circuit, a drive signal is generated by a level shifter in a manner similar to the above to drive second and third N-channel MOSFETs for generating an output signal having signal amplitude corresponding to the third power source voltage.

Semiconductor integrated circuit

The invention provides a technique that enables a correct discrimination of reception data, when the supply voltage of a semiconductor integrated circuit having a simultaneous bi-directional interface is decreased. The data transmission system is provided with input circuits constituting a simultaneous bi-directional interface by the number of reference voltages used. Each of the input circuits is supplied with a fixed reference voltage, the input circuit supplied with a higher reference voltage employs a differential amplifier with n-channel MOSFETs served as input differential devices, and the input circuit supplied with a lower reference voltage employs a differential amplifier with p-channel MOSFETs served as input differential devices, in which selectors switch the outputs of the two differential amplifiers in correspondence with the output data of their own. Thus, the system attains the reception data.

Data transmission system

Growing community of inventors

Tokyo, Japan

Shunsuke Toyoshima