Sony Computer Entertainment Inc.

Shunsaku Tokito

Atsushi Hayashi

Hiroshi Yoshihara

Chiaki Takano

Hiroaki Terakawa

Masaaki Nozaki

Atsushi Tsuji

Yuuki Fujiyama

Atsuo Mangyo

Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), comprising: inverting a state of data for input to one or more columns of the array; and storing the inverted data in one or more memory cells of the one or more columns.

Methods and apparatus for low power SRAM based on stored data

Processors arranged in a multi-processor configuration for substantially parallel operations receive their initialization data in order to start operations, such as graphics computations, real-time multimedia streaming, etc. Due to a change in the processing load, one or more processors might be deactivated. Subsequently, the load increases to such a level that requires all or some of the deactivated processors to be active again. In this case, the boot-up process of the entire system is not carried out as it would be time-consuming and wasteful; instead, responsive to a control signal only those processors that were previously in inactive mode are re-initialized by selecting a configuration data supplied by another processor, controller or any other intelligent programmable device. Alternatively, the configuration data may be accessed and retrieved from a local storage medium individually located in each processor, thereby re-booting only those inactive processors and without re-initializing the entire system.

Method and system for rebooting a processor in a multi-processor system

Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge, logic high voltage level during operations in which a logic low level is written into the anti-parallel storage circuit.

Methods and apparatus for improved write characteristics in a low voltage SRAM

Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge level during operations in which a logic one is read from the anti-parallel storage circuit.

Dual word line or floating bit line low power SRAM

Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), including: mirroring logic values of at least one of the bit lines to a global bit line; driving the global bit line to a pre-charge logic value in response to a clock signal that cycles at least one time during successive read and write operations to the memory cell; maintaining the global bit line at the pre-charge logic value during a write operation in which a logic value is written to the bit line that is opposite to the pre-charge logic value.

Methods and apparatus for low power SRAM using evaluation circuit

Methods and apparatus provide for pre-charging a bit line and a complementary bit line of an SRAM memory cell of the SRAM memory to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the memory cell.

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Austin, TX, United States of America

Shunsaku Tokito