Hitachi, Ltd.

Shunji Shimada

Osamu Yamashiro

Hiroshi Takahashi

Kenji Kawakita

Tsuneo Ito

Yoshikazu Hatsukano

Sakae Miki

Kenji Iimura

Harumi Wakimoto

Michio Hara

Kenichi Kimura

Kenichi Ohba

Kenjirou Yasunari

Akira Ikuta

Shigeo Ishii

A system of adding an operand address included in an instruction word to the contents of a modification register to obtain an effective address, wherein address data which designates each of a plurality of data tables constituted with prescribed storage capacity, is stored in a plurality of modification registers. Prescribed address data of one of the plurality of modification registers is selected based on the instruction word. The effective address for addressing the operand is obtained by adding the prescribed address data of the one of the plurality of modification registers to address data included in the operand address. The address data included in the operand address designates addresses which correspond to addresses of the plurality of data tables.

Operand address modification system

A constant-current circuit has a depletion type FET and a series circuit consisting of an impedance element and an enhancement type FET connected in parallel between two terminals. The gate electrodes of the respective FET's are connected to a juncture between the impedance element and the enhancement type FET, and current which flows through the depletion type FET is set to be sufficiently larger than a current which flows through the series circuit. The voltage across the enhancement type FET is made substantially equal to a threshold voltage thereof, whereby the constant current characteristics of such constant-current circuits are checked from being dispersed.

Constant-current circuit

A signal converter circuit for converting a binary signal delivered from a bipolar transistor logic circuit into another binary signal adapted for application to a MIS transistor logic circuit. The converter circuit comprises first, second and third stages; the first stage includes a source follower circuit, the second stage includes a series connection of a pair of parallel-connected MIS FETs and a switching MIS FET, and the third stage includes an inverter circuit. The output of the third stage is fed back to the gate of one of the pair of MIS FETs in the second stage so that the converter output has binary levels acceptable to a MIS logic circuit.

Signal converter circuit

A constant-current circuit comprising a first enhancement type FET, a depletion type FET having its drain and source connected to the drain and gate of the first enhancement type FET respectively, a second enhancement type FET having its drain and source connected to the gate and source of the first enhancement type FET and a series connection of two impedance elements having its ends connected to the source of the depletion type FET and to the source of the second enhancement type FET, the juncture between the two impedance elements being connected to the gate of the second enhancement type FET, whereby the constant-current characteristics of such constant-current circuits are checked from being dispersed.

In a gate input circuit for insulated gate field effect transistors, an insulated gate field effect transistor of depletion type is used, whose drain electrode (or source electrode) is connected to one terminal of a power source and whose source electrode (or drain electrode) is short-circuited with the gate electrode and connected to an input terminal of the gate input circuit through a resistor.

Gate input circuit for insulated gate field effect transistors

A driver circuit comprises an output circuit having a depletion type MOSFET and an enhancement type MOSFET connected in series with the depletion type FET. A voltage V1 is supplied to the drain of the depletion type FET and a voltage V2 is supplied to the source of the enhancement type FET, wherein .vertline.V1.vertline. &gt; .vertline.V2.vertline. &gt; .vertline.V th D.vertline., VthD being the threshold voltage of the depletion type MOSFET. A control signal is supplied directly to the gate of the enhancement type FET and, through an inverter, to the gate of the depletion type FET. As a result, a push-pull driver circuit using E/D MOSFETs is obtained.

Driver circuit for liquid crystal display using insulated gate FETs

For driving a plurality of memory cells, a driver circuit, connected to the word driver line of the memory cells, includes a resistive connection, connected between the word line and ground potential, for preventing the potential of the word line from floating. The driver circuit includes an enhancement-type switching MOSFET and a depletion type resistor MOSFET connected in series. By virtue of the connection of a gate of the depletion type MOSFET, the depletion type MOSFET is always turned on so that whether or not the switching type enhancement MOSFET is turned on, the common connection between the switching MOSFET and the resistive MOSFET will always be at a prescribed potential thereby preventing the word driver line from floating.

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Kodaira, Japan

Shunji Shimada