Elpida Memory, Inc.

Micron Technology Incorporated

Ps4 Luxco S.a.r.l.

Shunji Kuwahara

Hiroki Fujisawa

Mitsuaki Katagiri

Satoshi Isa

Raj K Bansal

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices

Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses

To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.

Semiconductor device having pull-up circuit and pull-down circuit

To include an output terminal, unit buffers, and plural output-wiring paths that respectively connect the unit buffers and the output terminal. The output wiring paths have individual output wiring sections individually allocated to corresponding unit buffers. Unit buffers corresponding to these output wiring paths are common output wiring sections shared by the output wiring paths, and are connected to the output terminal without via a common output wiring section having a higher resistance value than those of the individual output wiring sections. Accordingly, an deviation of impedance due to a parasitic resistance between the output terminal and the unit buffers is suppressed.

Semiconductor device having plural unit buffers constituting output buffer

To include two counter circuits that change impedances of two replica circuits, respectively, and an impedance adjustment control circuit that controls the counter circuits to update count values of the counter circuits. The impedance adjustment control circuit controls one of the counter circuits to finish updating the count value of the counter circuit in response to a change of the impedance of the corresponding replica circuit from a state of being lower than an impedance of an external resistor to a state of being higher than the impedance of the external resistor, and controls the other counter circuit to finish updating the count value of the other counter circuit in response to a change of the impedance of the other replica circuit from a state of being higher than the impedance of the former replica circuit to a state of being lower than the impedance of the former replica circuit. With this configuration, the adjust errors generated in the replica circuits are canceled.

Impedance control circuit and semiconductor device including the same

A calibration circuit includes: a replica buffer that drives a calibration terminal; a pre-emphasis circuit connected in parallel to the replica buffer; and an up-down counter that changes impedances of the replica buffer and the pre-emphasis circuit. A replica control circuit causes the replica buffer to conduct based on an impedance code, and a pre-emphasis control circuit causes the pre-emphasis circuit to conduct in an initial stage of a conducting period of the replica buffer. Thereby, even when an external resistor is shared among a plurality of semiconductor devices, for example, a voltage appearing in the calibration terminal can be stabilized at a higher speed.

Calibration circuit, semiconductor device including the same, and memory module

In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLKto both a hit determination circuit and a second clock gate circuit. The second clock gate circuitpasses through the first update clocks CLKuntil reception of a hit signal from the hit determination circuit and delivers second update clocks CLKto an up/down counter. The up/down counteris operated by the second update clocks CLK. With this structure, the second update clocks used for adjustment steps can be increased in number during the calibration period.

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Tokyo, Japan

Shunji Kuwahara