Renesas Electronics Corporation

Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Shunji Kubo

Atsushi Amo

Atsushi Hachisuka

Tatsuo Kasaoka

Yasuki Yoshihisa

Tetsuya Iida

Tatsuhiko Ikeda

Kouji Tanaka

Mikio Tsujiuchi

Koichi Ando

Masao Yamawaki

Hideyuki Tajima

Eiji Io

Atsushi Amoo

A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.

Semiconductor device

A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction from an ndrain region toward an nsource region. The plurality of trenches each have a conducting layer therein extending in the main surface in the direction from the ndrain region toward the nsource region.

Semiconductor device and method for manufacturing the same

An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the P+ type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW).

Semiconductor device and method for manufacturing same

A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (), an insulating layer () on the semiconductor substrate (), a plurality of contact plugs () in the insulating layer (), and an insulating layer () where capacitors (), a plurality of contact plugs (), barrier metal layers () and copper interconnections () are formed. Source/drain regions () in the upper surface of the semiconductor substrate () are electrically connected to the copper interconnections (). One of adjacent source/drain regions () in the upper surface of the semiconductor substrate () is electrically connected to the copper interconnection (), while the other is electrically connected to the capacitor ().

Semiconductor device and method of manufacturing same

In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.

Semiconductor device including a TCAM having a storage element formed with a DRAM

Semiconductor device having a capacitor and method of manufacturing the same

A memory cell part of a semiconductor substrate is formed with a cylindrical capacitor opening extending perpendicularly to the main surface of the semiconductor substrate. The cylindrical capacitor opening passes through a silicon oxide film, a silicon nitride film and another silicon oxide film in this order. A capacitor lower electrode, a dielectric film and a capacitor upper electrode are formed in the cylindrical capacitor opening along the surface of the cylindrical capacitor opening. The bottom surface of the cylindrical capacitor opening is formed below the main surface of silicon nitride film. Thus obtained is a semiconductor device capable of improving refreshability and soft error resistance.

Semiconductor device having a capacitor with increased capacitance

According to the present invention, a method for manufacturing a semiconductor device forms a cobalt silicide film on source/drain regions and and a gate electrode of transistors in the logic circuit region, making it possible to form a high-performance and highly integrated logic circuit.

Method for manufacturing a semiconductor device

A depression having a depth not exceeding 0.1 .mu.m is formed on the surface of an epitaxial layer. An internal base region is formed just below the depression. An external base region is formed outside the depression. The depression having the above depth can suppress electric field at the end of the internal base in the neighborhood of the junction between the internal base region and the external base region.

Growing community of inventors

Tokyo, Japan

Shunji Kubo