Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Shunji Inada

Norihiko Sugimoto

Takuji Hamada

Yoshinori Ohkura

Katsuhiko Yoneda

Kinshirou Oonishi

Shigeo Kuboki

Shinichiro Yamaguchi

Masakazu Okada

Masahiro Ueno

Tomoaki Aoki

Yoshinori Okura

Seiji Kamada

Hiroshi Tomizawa

Eiki Kondoh

Toshihiko Tominaga

Kazuhisa Inada

Nagatoshi Usami

Toshiyuki Katayama

A system for transmitting data in high precision by restricting a delay in data transmission time includes a hub. The hub receives through the transmission media a data frame transmitted from a communication device that has a transmission request among a plurality of communication devices, and relays the received data frame to a destination communication device based on a destination address included in the received data frame.

Data transmission method and system for hub-based network

In a data communication adapter apparatus for a digital data communication connected between a signal transmission path for transmitting both receive data and transmit data, and a host processor unit for producing frame data to output the frame data therefrom, an internal host bus is newly employed in the data communication apparatus irrelevant to the employment of a CPU dedicated bus, and the transmission/reception data generated and interpreted by the host processor is transferred via the internal host bus, a bus interface, and a system data bus between a transmission memory or a reception memory and a buffer memory. Furthermore, a reception memory (host dedicated reception memory) for storing only the reception data to be interpreted by the host processor is separately provided with another reception memory (CPU dedicated reception memory) for storing only the reception data to be interpreted by a CPU, one reception data to be interpreted by the CPU is once transferred from the transmission/reception control unit to the CPU dedicated memory and thereafter read out via the CPU dedicated bus under the control of the CPU, and the other reception data to be interpreted by the host processor is one stored in the host dedicated reception memory and then read out via the internal host bus and bus interface under the control of the host processor.

Data communication adapter and data communication terminal apparatus for

A system for transmitting data in high precision by restricting a delay in data transmission time, and including a hub. The hub receives through transmission media a data frame transmitted from a communication device that has a transmission request among a plurality of communication devices, and relays the received data frame to a destination communication device based on a destination address included in the received data frame.

A data communication system carries out transmission and reception of periodic data between a plurality of computers, and especially an improved data communication system which aims at more effective utilization of a system bus in each computer and which also aims at more effective utilization of a data transmission channel transmitting periodic data, so that the load imposed on the system bus during transfer of periodic data in each computer can be minimized, and the rate of occupation of the data transmission channel during transmission and reception of periodic data can also be minimized.

Cyclic data communication system

A data transmitting/receiving apparatus comprises a master clock signal and a slave clock signal which differ in phase with each other according to a basic clock signal. Serial data is input according to the produced master clock signal or slave clock signal, a protocol process is applied to the input serial data, and the serial data subjected to the protocol process is output according to the master clock signal or the slave clock signal. A start delimiter detecting signal is generated when a start delimiter indicating the first frame is detected in the input serial data and phases are exchanged between the master clock signal and the slave clock signal when there arises a shift on a bit boundary of the serial data when the start delimiter detecting signal is generated. The serial data is output according to the master clock signal or the slave clock signal having their phases exchanged with each other, thus the serial data is transmitted without delay despite a shift arising on the bit boundary of the serial data.

Clock generating apparatus, data transmitting/receiving apparatus and

In a method of controlling a buffer device, data are received from a communication transmission line, and the received data are written in a buffer device at a predetermined write rate. The data written from the buffer device are started to be read at a predetermined read rate. The quantity of data written and accumulated in the buffer device is compared with a predetermined threshold for a predetermined period from the read start point of time. When it is found as the result of comparison that the quantity of accumulated data is the same as or less than the threshold, the buffer device performs only write of data from the communication transmission line and, when the quantity of accumulated data is larger than the threshold, the buffer device performs both write of data from the communication transmission line and read of data out of the buffer device at the same time during a predetermined period.

Data communication system

Multi-network system for transmitting data among a plurality of stations, each of which is connected to one of transmission lines, a plurality of said transmission lines being connected with each other through bridge stations, in which the numbers of the transmission lines, with which in final destination station and the source station are connected respectively, are set as the destination address and the source address in the data frame to be sent; in the case where the bridge station receives a frame of data to be relayed between different transmission lines, the bridge station identifies the relay by the destination address, stores the data frame in a memory means storing data, which should be sent by the bridge station itself; attaches to the data to be relayed a flag, in which the relay indication is set, and to the data not to be relayed a flag, in which the relay indication is not set; and when the data are sent by said station, in the case where the flag attached to the data represents the relay, the data frame which has been received is sent without any change.

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Hitachi, Japan

Shunji Inada