Nippon Telegraph and Telephone Corporation

Shunji Honda

Shuzo Kato

Shuji Kubota

Katsuhiko Kawazoe

In a simple decoder which decodes convolutional codes of constraint length K and coding rate n/m, encoded data which is supplied thereto in steps of m bits are distributed, bit by bit, to m shift registers each having x=[(K-1)/(m-n)] series-connected shift stages. Here, [p] means the minimum integer equal to or larger than a real number p. The connection of n modulo-2 addition circuits to all the shift stages of all the shift registers is defined by n decoding generative vectors which define n decoding generative polynomials. The modulo-2 addition circuits perform modulo-2 additions of the outputs of the shift stages connected thereto and output n results of additions as decoded results of n bits. The n decoding generative vectors are selected from decoding generative vectors of N rows which are obtained as an inverse matrix of a square matrix whose elements are N.times.N coefficients which define N=mx convolutional code generating polynomials.

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Yokosuka, Japan

Shunji Honda