Shinko Electric Industries Co., Ltd.

Shunichiro Matsumoto

Tadashi Kodaira

Jyunichi Nakamura

Takeshi Chino

Hironari Aratani

Takanori Tabuchi

Kentaro Kaneko

Kazuhiko Ooi

Eisaku Watari

Junichi Nakamura

Katsuya Fukase

Kazuhiro Kobayashi

Kotaro Kodani

Hitoshi Kondo

Tomoyuki Shimodaira

Toyoaki Sakai

Toshihisa Yoda

Kiyotaka Shimada

Toshimitsu Omiya

Masako Sato

Ruofan Tang

A wiring board includes a single-layer insulating layer, and a single-layer interconnect layer embedded in the insulating layer, wherein an entirety of a first surface of the interconnect layer is exposed in a recessed position relative to a first surface of the insulating layer, and a second surface of the interconnect layer is partially exposed in a recessed position relative to a second surface of the insulating layer.

Wiring board and semiconductor device

A wiring board includes an insulating layer; and a wiring layer embedded in the insulating layer at one surface side of the insulating layer, one surface of the wiring layer being exposed from one surface of the insulating layer, the wiring layer including a first portion and a second portion whose width is wider than that of the first portion, one surface of the first portion and one surface of the second portion being flush with each other, and the first portion being thinner than the second portion.

Wiring board

A wiring substrate includes an insulating layer, a pad, and a solder resist layer. The insulating layer has a first surface formed with a first recess portion. The pad is embedded in the first recess portion. The pad includes a second surface and a third surface. The third surface that is located at a lower position than the first surface so as to expose an inner wall surface of the first recess portion. The pad is formed with a second recess portion in a center portion of the third surface. The solder resist layer is provided on the first surface. An adjacent portion of the first surface to a peripheral portion of the first recess portion is smaller in roughness than a region of the first surface peripheral to the adjacent portion of the first surface.

Wiring board and method for manufacturing the same

A wiring board includes a structure in which a plurality of wiring layers are stacked with insulating layers interposed therebetween, a plurality of pads for mounting an electronic component, the pads being formed on an outermost insulating layer on one surface side of the structure and exposed to the surface of the outermost insulating layer, and a recessed portion formed at a place corresponding to a mounting area for the electronic component. The recessed portion is formed in the outermost insulating layer at an area between the pads to which electrode terminals of the electronic component to be mounted are to be connected, respectively.

Wiring board, method of manufacturing the same, and semiconductor device

In a wiring board, a plurality of wiring layers and a plurality of insulating layers are alternately stacked. The wiring layers are electrically connected to one another through via holes formed in the insulating layers. The wiring board includes: a connection pad which is disposed on one of the wiring layers that is on the inner side of an outermost wiring layer; and an external connection terminal which is disposed on the connection pad, and which is projected from the surface of the wiring board. The external connection terminal is passed through the outermost wiring layer.

Wiring board, method for manufacturing the same, and semiconductor package

To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.

Package for semiconductor devices

To prevent the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a small strength. A package for semiconductor devices is formed as a laminate () of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole regions or some regions of the insulating resin layers (to) of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.

A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.

Multilayered substrate for semiconductor device

The invention relates a method for producing a multilayer circuit board () for a semiconductor device, comprising using a composite metal sheet () in which two metal sheets are combined, forming, on each side of the composite metal sheet, pads for connecting to a semiconductor element, the pads being made of a metal material which is substantially not etched by an etchant for the metal sheet, and an insulating layer having openings exposing the pads, forming, on the insulating layer, a wiring line layer () connected to the pads and having pads for connecting to another wiring line layer to be subsequently formed, subsequently fabricating a multilayer circuit board body () by necessary numbers of insulating layers and wiring line layers alternately formed, forming, on the outermost insulating layer of the multilayer circuit board body, an insulating layer provided with through-holes exposing pads for external connecting terminals, which are located on the outermost insulating layer, then dividing the composite metal sheet, to yield intermediates () each provided on one side of the metal sheet with the multilayer circuit board body, and etching the metal sheet at an area at which a semiconductor element is to be mounted to remove the material of the metal sheet at that area, to thereby form a frame () surrounding the area for the mounting of the semiconductor element.

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Nagano, Japan

Shunichiro Matsumoto