Sony Corporation

Texas Instruments Corporation

Hitachi, Ltd.

Other

Sony Semiconductor Solutions Corporation

Shunichi Sukegawa

Noriyuki Fukushima

Kenichi Shigenami

Shinji Bessho

Masayuki Hira

Tsutomu Takahashi

Yukihide Suzuki

Hiroshi Takahashi

Keishi Inoue

Yasushi Takahashi

Tatsuo Shimizu

Takeo Sekino

Shinichi Toi

Tsugio Takahashi

Koji Arai

Makoto Saeki

Masanori Hosomi

Shunji Maeda

Yutaka Higo

Koichi Abe

Junichi Ishibashi

Kouji Arai

Taku Umebayashi

Hidetoshi Iwai

Takashi Yokoyama

Takumi Nasu

Mamoru Kudo

Tadashi Tachibana

Motoshige Okada

Masaya Muranaka

Katsuo Komatsuzaki

Takashi Inui

Tetsuya Saeki

Chisa Makimura

Hugh Pryor McAdams

Hiep V Tran

Hiroyuki Yoshida

Yoshikazu Nitta

Takeshi Sakai

Kiyoshi Nakai

Masayuki Nakamura

Kenichi Okumura

Hajime Hosaka

Masayasu Kawamura

Kanehide Kenmizaki

Hiromi Matsuura

Yasuhito Ichimura

Shigeki Numaga

Yoritaka Saitoh

Ken Saitoh

Kohji Arai

Tathunori Mushya

Atsuya Tanaka

Shiyuzo Shiozaki

Noriaki Kubota

Yoojoon Moon

Hiroyuki Fujiwara

A solid state image sensor of the present disclosure includes: a first semiconductor substrate provided with at least a pixel array unit in which pixels that perform photoelectric conversion are arranged in a matrix form; and a second semiconductor substrate provided with at least a control circuit unit that drives the pixels. The first semiconductor substrate and the second semiconductor substrate are stacked, with first surfaces on which wiring layers are formed facing each other, the pixel array unit is composed of a plurality of divided array units, the control circuit unit is provided corresponding to each of the plurality of divided array units, and electrical connection is established in each of the divided array units, through an electrode located on each of the first surfaces of the first semiconductor substrate and the second semiconductor substrate, between the pixel array unit and the control circuit unit.

Stacked substrate solid state image sensor

Disclosed herein is a solid state imaging device including a support substrate; an imaging semiconductor chip having a pixel array disposed on the support substrate; and an image processing semiconductor chip disposed on the support substrate, wherein the imaging semiconductor chip and the image processing semiconductor chip are connected by through-vias, and interconnects formed on the support substrate.

Semiconductor device, solid-state imaging device, and camera system

A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

Semiconductor apparatus, method of manufacturing semiconductor apparatus, method of designing semiconductor apparatus, and electronic apparatus

Solid state image sensor comprising stacked substrates, semiconductor device, and electronic device

An imaging apparatus is configured of a first structureand a second structure, in which the first structureincludes a first substrate, a plurality of temperature detection devicesformed on the first substrateand configured to detect a temperature on the basis of an infrared ray, drive lines, and signal lines, the second structureincludes a second substrate, and a drive circuit provided on the second substrateand covered with a covering layer, the first substrateis bonded to the covering layer, a cavityis provided between each temperature detection deviceand the covering layer, and the drive linesand the signal linesare electrically connected to the drive circuit.

Imaging apparatus with infrared-based temperature detection devices

The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat. A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.

Memory cell structure, method of manufacturing a memory, and memory apparatus

The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.

Semiconductor device, solid-state image sensor and camera system

Solid state image sensor, semiconductor device, and electronic device

Growing community of inventors

Ibaraki, Japan

Shunichi Sukegawa