Sony Corporation

Shunichi Shibuki

Kyoko Izuha

Takashi Sakairi

Tatsushiro Hirata

Disclosed herein is a presumably defective portion decision apparatus, including: an arithmetic operation section configured to divide a level difference included in level difference data which indicate a level difference distribution on the surface of a semiconductor device into two or more unit level differences in the depthwise direction of the level difference and determine, for each of the unit level differences obtained by the division, a relationship between the height of a contour line at a level difference position of an upper face and an area of an opening surrounded by the contour line to decide presence or absence of a presumably defective portion.

Presumably defective portion decision apparatus, presumably defective portion decision method, fabrication method for semiconductor device and program

A solid-state imaging device includes a semiconductor layer where a pixel is formed in a pixel region and a semiconductor element is formed in a side opposite to where incident light is incident, a wiring layer provided on the semiconductor layer to cover the semiconductor element, a support substrate provided to oppose the wiring layer in a wiring layer surface opposite to the semiconductor layer, and an adhesion layer which adheres the wiring layer and the support substrate, where the wiring layer includes a pad electrode and an opening is formed so the pad electrode is exposed, a convex section is provided where the pad electrode is formed in at least a wiring layer surface opposing the support substrate or a support substrate surface opposing the wiring layer, and the adhesion layer is formed thinner at the formation portion of the pad electrode than a portion of the pixel region.

Solid-state imaging device, manufacturing method thereof, electronic apparatus, and semiconductor device

A method for manufacturing a semiconductor device includes the steps of reading physical layout data of a circuit to be manufactured and performing calculation to modify a pattern width in the physical layout data by a predetermined amount; reading a physical layout and analyzing a pattern that is predicted to remain as a step difference of a predetermined amount or more in a case where a planarization process is performed on a planarizing film on a pattern by a quantitative calculation by using at least one of a density of patterns, a pattern width, and a peripheral length of a range of interest and a range in the vicinity of the range of interest; and reading data of the pattern that is predicted to remain as a step difference, and making a correction to a layout in which a step difference of a predetermined amount or more does not remain.

Method, apparatus and program for adjusting feature dimensions to compensate for planarizing effects in the generation of mask data and manufacturing semiconductor device

Growing community of inventors

Kumamoto, Japan

Shunichi Shibuki