Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

The University of Tokyo

Shunichi Kuromaru

Tsuyoshi Nakamura

Junji Michiyama

Tomonori Yonezawa

Masahiro Oohashi

Koji Okamoto

Yasuo Kohashi

Mana Hamada

Masayoshi Tojima

Toshihiro Moriiwa

Kazuhiro Watanabe

Tadanori Tezuka

Tsutomu Sekibe

Masatoshi Matsuo

Hitoshi Fujimoto

Masaaki Kondo

Miki Arita

Hiromasa Nakajima

Masashi Imai

Takashi Nanya

Hiroki Ootsuki

Nassu Tomoyuki Bogdan

A request change unit outputs a command as a request under control of a judgment control unit. A response condition determination unit determines a condition that is to be matched by a correct response which is to be returned from the other device-in-communication in reply to the command if the other device-in-communication operates in conformity with a protocol. A check unit checks a response received from the other device-in-communication in reply to the command, against the condition. If the received response does not match the condition but is correctable to match the condition as a result of the check, a response correction unit corrects the received response to match the condition under control of the judgment control unit.

Communication method and communication device

The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.

Processor

It is decided whether a first source data from the memoryis a data which is to be subjected to arithmetic or not by a state flag detection means, the result of the decision is retained as a state flag, and it is decided by a condition decision meanswhether or not the state flag satisfies a condition for performing the arithmetic. A control meanscontrols whether an ALUshould perform the arithmetic or not on the basis of the condition satisfaction/dissatisfaction information.

Conditional vector arithmetic method and conditional vector arithmetic unit

The image processing apparatus according to the present invention comprises: DMA control meanshaving image input/output processing means, an external memory, DMA setting holding means, address generating means, DRAM control means, DMA request generating means, and DMA request adjusting means; a processorincluding encoding/decoding processing means; and a DMA busas shown in FIG. In the image processing apparatus so constructed, a transfer data group which can be previously subjected to DMA scheduling is divided into burst transfer units, and the DMA request generating means periodically issues the DMA request in the burst transfer units and performs DMA of the transfer data which cannot be subjected to the DMA scheduling during the period that the DMA of the transfer data is not performed, thereby avoiding concentration of specific DMA.

Image processing device

Arithmetic unit

A deblocking filter arithmetic apparatus and a deblocking filter arithmetic method employed for removing block noises generated at decoding image data which have been subjected to the encoding process. Successive pixel data are input to eight arithmetic blocks () every two data, a filtering processing arithmetic for removal of the block noises is carried out in parallel so as to conclude the filtering processing arithmetic in a unit of the combination of two arithmetic blocks in an order successively, thereby the pixel data obtained by performing the filtering processing are output by a pipeline system in a unit of the combination of the arithmetic blocks from an output selection circuit ().

Deblocking filter arithmetic apparatus and deblocking filter arithmetic method

Apparatus and method for data transmission while performing encoding processing on a non-limited moving vector mode, which avoids an increase in required memory capacity and a reduction in processing load, the apparatus comprising a two dimensional address generating unit for generating an access address of an external memory and an address control unit for administrating the horizontal position and the vertical position of the extended logical space and generating an operation authorizing signal for the two dimensional address generating unit, and the two dimensional address generating unit and the address control unit are operated in relation to each other so that an access address to outside the effective video data region is controlled to be an address of a pixel data at the periphery of the effective video data region, thereby reducing the extended region in the external memory.

Video processing apparatus for performing address generation and control, and method therefor

An object of the present invention is to provide an image processing apparatus in which a delay from start of image data input to start of coding is small, the capacity of a temporary storage device used for temporarily storing the image data to be coded is small, and the possibility of discarding the image data is low even when coding is delayed and, therefore, the image quality is hardly degraded. Since this apparatus is provided with a flag generator for generating control information according to the processing status, input/output of the image data in/from the temporary storage device is performed for each unit amount, and storage and coding of the image data are executed according to the control information.

Image processor and image processing method

An image processing apparatus according to the present invention comprises a general arithmetic circuit comprising a program control circuit , a first address generator , a first data memory , a first pipeline operation circuit , a second address generator , a second data memory and a second pipeline operation circuit , and a dedicated arithmetic circuit comprising a control circuit , a first dedicated pipeline operation circuit , a second dedicated pipeline operation circuit , . . . , an N-th dedicated pipeline operation circuit , as shown in FIG. The arithmetic unit having the above-described structure, for example, can realize an arithmetic unit which can be applied to various applications. Further, considering the age of IP (Intellectual Property) which will come in the future, the arithmetic unit can exhibit the flexibility toward the applications.

Processor and image processing device

Filter arithmetic device

A high-function address generating apparatus is realized which generates a memory address that can access a multidimensional area without running over a memory area specified by a user. Continuous addressing domain which is determined by a top address and a final address is set by an addressing domain setting means , an address is generated by a two-dimensional address generating means , the address in a two-dimensional area is compared with the final address and the top address by a first and a second comparing means and , respectively, whether it runs over the addressing domain or not is judged by an address correction means , and an address running over is corrected so as to not run over.

Address generating apparatus and motion vector detector

Arithmetic device

Growing community of inventors

Fukuoka, Japan

Shunichi Kuromaru