Matsushita Electric Industrial Co., Ltd.

Shunichi Kurohmaru

Masatoshi Matsuo

Tomonori Yonezawa

Mana Hamada

Miki Arita

Masayoshi Toujima

Masahiro Ohashi

Mana Saishi

Yasuo Kouhashi

Yasuo Kohashi

Hitoshi Fujimoto

An image decoding unit comprises a decoding unit, a data memory unit, a reconstruction unit, and a frame memory. The decoding unit includes an entropy decoder, a motion compensator, an inverse quantizer, and an inverse DCT unit. The data memory unit includes a data memory A and a data memory B. In the middle of the data transfer from the data memory unit to the frame memory, the reconstruction unit that inputs intermediate data of decoding and outputs reconstructed image data is provided; thereby, the processing of generating the reconstructed image data and the processing of storing the reconstructed image data into the frame memory can be performed in parallel. By the structure, a high-speed processing of image reconstruction can be performed.

Image decoding unit, image encoding/ decoding devices using image decoding unit, and method thereof

A motion vector detection apparatus for detecting a motion vector by performing block matching between a target block including a plurality of pixels in a current image, and a reference block including a plurality of pixels in a predetermined reference area in a past image that is previous to the current image, the apparatus including a first address generator for generating addresses of data in the target block and addresses of data in the reference area; a first storage unit for holding data of the reference area designated by the first address generator; a second storage unit for holding data of the target block designated by the first address generator; a second address generator for generating addresses of data to be outputted from the first storage unit and the second storage unit; and a motion vector detector for detecting a motion vector by using the data outputted from the first storage unit and the data outputted from the second storage unit; wherein the motion vector detector subtracts the absolute values of differences in pixel data between the reference block and the target block, one by one, from a threshold value, and when the result of subtraction becomes negative, the motion vector detector stops calculation of the sum of absolute differences in the corresponding position.

Motion vector detection apparatus for performing checker-pattern subsampling with respect to pixel arrays

A motion vector detection apparatus for detecting a motion vector by performing block matching between a target block including a plurality of pixels in a current image, and a reference block including a plurality of pixels in a predetermined reference area in a past image, the apparatus including a first address generator for generating addresses of data in the target block and addresses of data in the reference area; a first storage unit for holding data of the reference area designated by the first address generator; a second storage unit for holding data of the target block designated by the first address generator; a second address generator for generating addresses of data to be outputted from the first storage unit and the second storage unit; and a motion vector detector for detecting a motion vector by using the data outputted from the first storage unit and the data outputted from the second storage unit. The second address generator is for performing subsampling on the addresses of the data to be outputted from the first storage unit and the second storage unit so that the addresses are sampled in a checker pattern with respect to pixel arrays corresponding to images of the reference block and the target block. Therefore, the amount of data to be processed is reduced, resulting in increased processing speed and reduced power consumption.

Motor vector detection apparatus for performing checker-pattern subsampling with respect to pixel arrays

An operating unit operates candidate operation data Da, Db. The candidate operation data Da, Db are contained in two source memories, respectively, or alternatively in one of the two source memories. An address-generating unit generates an address signal Aa and read enable signals RE, REin connection with the candidate operation data Da. The address-generating unit further generates an address signal Ab and read enable signals RE, REin connection with the candidate operation data Db. Thus, data output from the source memory is controlled with each data to be operated, not with each of the source memory. As a result, data transfer-caused loads can be suppressed. This feature provides a processor having enhanced performance, and further reduces electric power that the processor consumes.

Processor and storage apparatus

For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.

Arithmetic unit and data processing unit

A multiplication method and a multiplication circuit, wherein a multiplicand is multiplied by a multiplier using a multiplication process, the result of the multiplication is added by an addition process to a rounding signal to be output from a rounding signal generation process, and the result of the addition, i.e., a multiplication result obtained after rounding, is stored in a register. By a barrel shifter, the multiplication result obtained after rounding stored in the register is shifted by a bit count indicated by a shift bit count signal. The shift bit count signal output from an instruction control process is input to the barrel shifter and a rounding signal generation process. The rounding signal generation process generates a rounding signal on the basis of the shift bit count signal indicating the bit count used to shift the multiplication result after rounding. By carrying out a rounding process in the addition process by using the rounding signal, the rounding process can be carried out at an appropriate position desired by the user without increasing instruction code or storage.

Multiplication method and multiplication circuit

A multiplication method and a multiplication circuit, wherein a multiplicand is multiplied by a multiplier by using a multiplication means, the result of the multiplication is added by an addition means to a rounding signal to be output from a rounding signal generation means, and the result of the addition, i.e., a multiplication result obtained after rounding, is stored in a register. By a barrel shifter, the multiplication result obtained after rounding stored in the register is shifted by a bit count indicated by a shift bit count signal. The shift bit count signal output from an instruction control means is input to the barrel shifter and a rounding signal generation means. The rounding signal generation means generates a rounding signal on the basis of the shift bit count signal indicating the bit count used to shift the multiplication result after rounding. By carrying out a rounding process in the addition means by using the rounding signal, the rounding process can be carried out at an appropriate position desired by the user.

A bus switch is connected among an input buffer memory, a data memory, and an encoding unit, to select between a first bus connection of the input buffer memory and the data memory and a second bus connection of the data memory and the encoding unit. A data transfer control unit controls the bus switch to select the first bus connection in response to a data request signal from the encoding unit, controls the process of reading from the input buffer memory and the process of writing into the data memory, controls the bus switch to select the second bus connection upon completion of the transfer of one unit of image data, and sends a transfer completion signal in order of causing the encoding unit to start performing encoding processing. This makes it possible to transfer image data from the input buffer memory to the data memory at high speed.

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Fukuoka, Japan

Shunichi Kurohmaru