Fujitsu Corporation

Fujitsu Semiconductor Limited

Spansion Llc.

Kyocera Kinseki Corporation

Shunichi Ko

Takashi Arai

Akira Shimamura

Hideo Nunokawa

Koichi Mita

Takuya Terasawa

Koji Mikami

Naoya Komada

Hiroyuki Abe

Nobuhiko Akasaka

Tomonari Morishita

Miki T Suzuki

Fukuji Kihara

Hideshi Fujishima

Kiyoko Honda

Shinichi Okamoto

Hiroshi Haibara

Hiroshi Ookawa

Akihiro Fujisuka

A signal receiver apparatus includes a waveform shaping data storage device storing waveform shaping data of a signal transmitted with a given timing from a signal transmitter device of a plurality of signal transmitter devices which are coupled to the signal receiver apparatus for each of the plurality of signal transmitter devices, and a waveform shaping device reading waveform shaping data of the signal transmitter device in the plurality of signal transmitter device from the waveform shaping data storage device when a signal from the signal transmitter device is received, and shaping a waveform of a received signal from the signal transmitter device.

Signal receiver apparatus and waveform shaping method

A transmitting/receiving system includes a control field controlling a transmitting priority of a dynamic slot is included in each communication cycle, and a node of the transmitting/receiving system sets control information including a preferential usage request for a dynamic slot that the node transmits in the control field and notifies all nodes in the transmitting/receiving system of the preferential usage request for the dynamic slot.

Transmitting/receiving system, node and communication method

A microcontroller is disposed on a receiving part of a wireless system in order to process a demodulation signal generated by a receiver circuit, and includes a memory and a CPU. The memory stores a control program of the microcontroller. The control program thereof includes a dual loop routine for an operation in reception standby mode. The dual loop routine has a first loop and a second loop included in the first loop. The CPU has an instruction set consisting of a plurality of instructions, and executes the instructions according to the program stored in the memory. The CPU executes an instruction irrelevant to an operation when the microcontroller is in reception mode during the second loop a number of times. The number of times is at least such that noise caused by the repetition of the second loop is lowered below a desired level.

Microcontroller

An object is not only to contribute to reduction in current consumption but also to advance actuation of a system required in a camera, an on-vehicle electric component, etc. by shortening a waiting time for stabilization of oscillation. An oscillator having an inverting amplifier inverting and amplifying an input signal and outputting it, a resonator connected to between an input and an output terminals of the inverting amplifier, a feedback resistance connected in parallel to the resonator, and an output circuit outputting a first clock signal based on a signal of an on-load parallel resonance frequency or a parallel resonance frequency oscillated by the resonator, the inverting amplifier and the feedback resistance to a function block is provided.

Oscillator and semiconductor device

Paying attention to the difference between a subsequently inputted analog signal and a reference signal which is an analog signal converted to the digital signal immediately before for instance, changing timing dynamically for converting the analog signal to the digital signal, and converting an analog signal sampled at the timing of changing dynamically to a digital signal.

Analog/digital conversion method and analog/digital conversion circuit

A zero transition voltage and a full transition voltage are inputted into the A/D converter, digital converted values of these voltages are fed back to a device fluctuation correction circuit and H side and L side reference voltages AVRH and AVRL are determined so as to obtain digital outputs corresponding to the respective transition voltages. Also, the digital output of the A/D converter is fed back to a high resolution corresponding circuit and a difference between AVRL and AVRH is decreased to be half as before by changing AVRL or AVRH according to an analog input voltage applied to the A/D converter and A/D conversion is performed again. By repeating this operation, significant bit values are obtained. A merge circuit merges the significant bit values with less significant bit values outputted from the A/D converter.

A/D conversion device and A/D converter error correction device

Growing community of inventors

Kawasaki, Japan

Shunichi Ko