Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Renesas Electronics Corporation

Keio University

Shunichi Iwata

Toru Shimizu

Mitsugu Satou

Ken Sakamura

Takashi Nasu

Shigeo Mizugaki

Takeshi Kataoka

Tatsuya Enomoto

Toshio Doi

Sugako Otani

Fumitaka Fukuzawa

Toyohiko Yoshida

Hiromichi Yamada

Tadahiro Kuroda

Teppei Hirotsu

Osamu Yamamoto

Hisakazu Sato

Teruaki Sakata

Yuichi Nakao

Kesami Hagiwara

Yoshikazu Kiyoshige

Yutaka Takikawa

Toshio Kishi

Hiroki Ishikuro

Yoshihiro Shimizu

Akihiko Tomita

Yoichi Takahata

Toshihiko Sugahara

A pulse transmission technique is used for wireless communication between a microcomputer () having a debugging support circuit () and a debugger (). The pulse transmission technique is based on magnetic field coupling between a first coil () provided for the microcomputer and a second coil () coupled with the debugger. During an initialization operation, the microcomputer performs a process of configuring a communication condition of the wireless communication to perform the wireless communication. The microcomputer awaits control from the debugger when the microcomputer establishes communication with the debugger. The debugger awaits establishment of the communication and proceeds to control of the microcomputer in accordance with the wireless communication. It is possible to provide contactless interface for system debugging without the need for a large antenna or a large-scale circuit for modulation and demodulation.

System debugging method, system debugging equipment, processor, wireless-communications interface IC and interface method thereof

A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.

Microcontroller and RAM

In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit. A high-speed access is made from the second processor to the second local memory via the second local bus. The second local memory is also accessed from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit and from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit.

Data processing system

A microcomputer according to the present invention includes: collecting unit for generating and collecting a series of trace information for each execution process of a program to be evaluated in a preset sampling period for a predetermined number of repetitions; outputting circuit for outputting the series of the trace information for each repetition; and decimating circuit for deleting any of the trace information collected at each repetition so that the outputting circuit can output all of the trace information to be collected within the sampling period when the collecting circuit has finished repetitive collection process.

Microcomputer and debugging system

A microcomputer comprises a serial interface for receiving a debugging program applied thereto from a debugging tool, a register for holding an instruction code included with the debugging program, which is applied to the microcomputer via the serial interface, and a central processing unit or CPU for executing the instruction code held by the first register to debug the microcomputer. The microcomputer can further comprise a buffer for holding one or more instruction codes supplied thereto from the register. The CPU can execute each of the plurality of instruction codes held by the buffer. Preferably, the serial interface is a JTAT (Joint Test Action Group) interface.

Microcomputer which can execute a monitor program supplied from a debugging tool

A microcomputer of the present invention permits a direct control of a rewrite operation on an internal flash-memory to enhance the efficiency of a debugging operation. The microcomputer has a first storage means that stores a program for rewriting data into an internal flash memory, a second storage means that stores internal flash information about the internal flash memory, an interface that makes a connection to a debugging tool, and a CPU. The CPU allows reading of the internal flash information by the debugging tool through the interface, receiving of write data based on the internal flash information from the debugging tool through the interface, and rewriting of the write data as new contents into the internal flash memory in accordance with the program for rewriting data into the internal flash memory.

Microcomputer including program for rewriting data in an internal flash memory

Exemplary embodiments of the present invention are directed toward a technique which facilitates the process instruction codes in processor. According to the present invention, a memory device is provided which comprises a plurality of 2N-bit word boundaries, where N is greater than or equal to one. The processor of the present invention executes instruction codes of a 2N-bit length and a N-bit length. The instruction codes are stored in the memory device is such a way that the 2-N bit word boundaries contains either a single 2N-bit instruction code or two N-bit instruction codes. The most significant bit of each instruction code serves as a instruction format identifier which controls the execution (or decoding) sequence of the instruction codes. As a result, only two transfer paths from an instruction fetch portion to an instruction decode portion of the processor are necessary thereby reducing the hardware requirement of the processor and increasing system throughput.

Processor for executing instruction codes of two different lengths and device for inputting the instruction codes

For a processor having instruction codes of two instruction lengths (16 bits and 32 bits), methods of locating the instruction codes are limited to two types: (1) two 16-bit instruction codes are stored within 32-bit word boundaries, and (2) a single 32-bit instruction code is stored intactly within the 32-bit word boundaries. A branch destination address is specified only on the 32-bit word boundary. The MSB of each instruction code serves as a 1-bit instruction length identifier for controlling the execution sequence of the instruction codes. This provides two transfer paths from an instruction fetch portion to an instruction decode portion within the processor, achieving reduction in code side and in the amount of hardware and, accordingly, the increase in operating speed.

A central processing unit (CPU) having a built-in dynamic random-access memory (DRAM) with exclusive access to the DRAM when the CPU performs an interlock access to the DRAM. A memory controller prevents the DRAM from being externally accessed while the CPU is performing the interlock access. When the memory controller receives an external request for accessing the DRAM during a time when the CPU is performing an interlock access to the DRAM, the memory controller outputs a response signal indicating that external access to the DRAM is excluded or inhibited. The request signal can be a hold request signal for requesting a bus right or can be a chip select signal. The response signal can be a hold acknowledge signal or a data complete signal. The memory controller can be switched to and from first and second lock modes, where hold request and hold acknowledge signals are used during the first lock mode and chip select and data complete signals are used in the second lock mode.

Computer system and semiconductor device on one chip including a memory

An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are outputted from an output terminal to the outside of a chip, as a space identifier for indicating which of an integrated ROM space, an integrated RAM space, and the external space is accessed by a currently executed program. A part of an address generated by the CPU is used so that the space which is accessed by the currently executed program is known from the outside in real time without requiring an external hardware.

Microcomputer for accessing a memory outside the chip by using an

In a semiconductor integrated circuit, a CPU (2), a DRAM (3), and a bus controller (5) are mounted on a same semiconductor chip. The bus controller (5) has a refresh control circuit (7, 70) including a refresh request circuit to output a refresh request at a constant timing, a forced refresh request circuit to output the refresh request at an optional timing that is different from the constant timing, and a refresh request stop circuit to output the refresh request forcibly.

Semiconductor integrated circuit having DRAM mounted on semiconductor

When a CPU (1) writes '10' into a register (RG) provided in a controller (5), an AND gate (10) receives a CPU clock mask signal (CMS1) having the logic of '0' by one of its input terminals and accordingly cuts off the supply of a clock signal CLK to the CPU (1). Then, the CPU (1) is suspended, thereby reducing power consumption of the CPU (1). To return out of this state, a user has only to input an interrupt request to the controller (5) through a terminal (T1). Receiving the request, the controller (5) outputs the CPU clock mask signal (CMS1) having the logic of '1' to one of the input terminals of the AND gate (10) so as to supply the CPU (1) with the clock signal (CLK) again. Upon restarting the supply of the clock signal (CLK), the CPU (1) starts an operation to implement the interrupt request. With this configuration, an integrated circuit device including a control circuit for controlling operations of a processing circuit and a memory circuit with excellent operability can be provided.

Integrated circuit device with a memory that preserves its content

A data processor having a string operation instruction and a bit map operation instruction, and comprises a bus interface unit 157 which inputs/outputs data by the burst transfer function, and an integer operation unit 155 building-in a main ALU and a sub-ALU, wherein data is repeatedly transferred to/from an external memory via a data bus 102 in unit greater than a width of the data bus 102. Further, is can be accessed in a high speed by the block transfer in the burst mode to efficiently execute the above instructions, therefore the data string and bit map data can be executed quickly even when a low-cost slow memory system is connected thereto.

Data processor

A data processor being provided with a microdecoder which decodes instruction codes comprising two operation code parts, a source operand specifying part and a destination operand specifying part, wherein an optional bit area of source data (a register of a general register file or a memory) is inserted in an optional bit area (determined by the value of the first operation code part) of a destination register according to the decoding result, and an optional bit area (determined by the value of the second operation code part) of a source register is extracted and stored in an optional bit area of destination (a register of the general register file or the memory), thereby making it possible to 'process the insertion and extraction operations to and from optional byte positions of registers' at a high speed with short instruction code size.

Data processor and control circuit for inserting/extracting data to/from

A shift circuit 213 used in arithmetic operations is provided with the shift width generating circuit 217 which generates a shift width data from lower bits of an access address and an access size, and a circuit is provided to generated data comprising the first select output circuit 214, the third select output circuit 216 and the like which generate a data by merging byte by byte selected from either an output of the shift circuit 213 or a value of a register of a register file 210 according to the combination of the lower bits of the access address and the access size. It is possible to align the data in the shift circuit 213 which is provided for the purpose of arithmetic operations, and exclusive alignment circuit is made unnecessary thereby enabling it to reduce the amount of hardware.

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Tokyo, Japan

Shunichi Iwata