Kabushiki Kaisha Toshiba

Shunichi Ishiwata

Keiri Nakanishi

Masato Sumiyoshi

Takashi Miyamori

Ryuji Hada

Katsuyuki Kimura

Yasuki Tanabe

Takaya Ogawa

Takahisa Wada

Yoshiro Tsuboi

Akira Moriya

Shuou Nomura

Hajime Matsui

Atsushi Mochizuki

Kazuyo Kanou

Shinichiro Koto

Atsushi Matsumura

Youhei Fukazawa

Yoshinori Shigeta

Hiromitsu Nakayama

Shuo Nomura

According to one embodiment, an image output device includes a buffer into which video information input in stream data is written per block, a determination unit configured to determine whether the buffer is in an overflow state due to slow reproduction, and a buffering control unit configured to switch a buffering pattern of the video information based on a determination result of the determination unit.

Image output device, image output method, and recording medium

A moving image player device of the present invention includes an interpolated image generating unit that generates an interpolated frame corresponding to a time between two adjacent input frames using two input frames among the plurality of input frames, and a video playing unit that detects a scene change in the video, outputs the plurality of input frames or the interpolated frames in time series based on the detection result, and plays the video at an arbitrary playing speed. When the scene change is detected, the video playing unit skips a display of the interpolated frames corresponding to time between an input frame at the end of a first scene and an input frame at the head of a second scene, and displays an input frame of the second scene or the interpolated frame after the input frame at the end of the first scene or the interpolated frame.

Moving image player device

According to a moving-image playback device of an embodiment of the invention, a frame rate control circuit uses an input interval Tc of a plurality of input images in an input video, a display interval Td of a plurality of display images in a display video, and a time extension magnification N of the display video with respect to the input video as inputs and that outputs the number 'm' of images of the same content and a constant 'n' greater by one than the number &#x201c;a&#x201d; of interpolation images which are each inserted between the input images. The frame rate control circuit outputs the number &#x201c;m&#x201d; of images and the constant &#x201c;n&#x201d;, which are determined based on a combination (m, n) of a natural number for satisfying an equation of n&#xd7;m=N&#xd7;Tc/Td, to the interpolation image generation circuit.

Moving-image playback device

An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

Image processor and command processing method

A moving image compression-coding device has a pixel determination module configured to determine whether a color of each pixel in a macro block having a plurality of pixels in an input image is a predetermined color, a pixel counter configured to count a number of the pixels having the predetermined color in the macro block, a macro block determination module configured to determine whether a color of the macro block is considered to be the predetermined color according to the count result, and a compression-coded data generator configured to compression-code the input image with a compression ratio depending on the determination result.

Moving image compression-coding device, method of compression-coding moving image, and H.264 moving image compression-coding device

According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

Compiling device and compiling method

An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

Image processing apparatus and image processing system

A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

Memory controller

A video coding device includes: a detecting unit configured to detect a foreground region, a background image and a shadow region reflected on the background image by the foreground region in an input picture; a shadow information compressing unit configured to perform a compression process to compress the information quantity of the shadow region; and a coding unit configured to code the foreground region, the background image and the information on the shadow region subjected to the compression process.

Video coding device, video decoding device and video encoding method

An image coding and decoding apparatus which can produce an improved amount of the effective data per time unit especially in a case where the image data are processed in the field unit. The apparatus includes: a subtracting unit which subtracts a reference image signal from an input image signal; a intra-frame coding unit which codes the image signal sent from the subtracting unit, and data on a reference image signal; and an inter-frame prediction unit which performs an image prediction process among previous or future image data and which sends the reference image signal to the subtracting unit and the intra-frame coding unit, wherein the apparatus is characterized in that the inter-frame prediction unit includes an input-output circuit in which pixel data of luminance signals are separated from those of color signals, and the thus separated pixel data are arranged in a single row of a horizontal direction as a minimum unit, so that the amount of effective data accessible in a time unit can be significantly increased in the course of processing data in the field unit.

Growing community of inventors

Chiba, Japan

Shunichi Ishiwata