Samsung Electronics Co., Ltd.

Shung-hyun Cho

Noh-byung Park

Hee-Duck Park

Jung-Gyu Lim

Tae-Soo Kim

Sang-jin Lee

Kwang-Yong Lee

Chang-ho Lee

Myoung-ho Kim

Cheon-moo Lee

Eun-kyung Kim

Su-young Kim

Jeong-Woo Hong

Noh-Buyng Park

A computer system security apparatus and a security method thereof, the apparatus including a recognition unit to recognize identification information of a user; an operation unit to produce a result value by executing a predetermined operation on the identification information of the user and unique identification information of the computer system; and a main control unit to execute a booting of the computer system according to whether a preset password of the computer system and the result value are the same.

Security apparatus for computer system and method thereof

A method and device for controlling a CPU stop clock interrupt of a computer system. The device includes an idle detector and a control processor. A CPU having a stop clock interrupt mode receives a stop clock interrupt signal and sets up and clears the stop clock interrupt mode according to a logic state of the stop clock interrupt signal. The control processor receives a signal representing an idle condition of the computer system from the idle detector, a signal for enabling idle detector control of the CPU stop clock interrupt mode and a signal for forcing the CPU to resume a normal mode by clearing the stop clock interrupt mode. The idle condition can be defined by a computer user according to a selection of predetermined times during which no user inputs are received by the computer system. The method includes monitoring the idle condition of the computer system, monitoring the signal for enabling idle detector control of the stop clock interrupt mode and monitoring the signal for forcing the CPU to resume a normal mode by clearing the stop clock interrupt mode. The stop clock interrupt signal is output having a logic state corresponding to the logic combination of the monitored signals.

Method and device for controlling a CPU stop clock interrupt

A computer system includes: a host unit, a power management system, a data backup power supply, a switching mode power supply, an auxiliary storage unit and a memory. The power management system generates a hibernation signal when an event is not generated from peripheral devices for a predetermined time period, a battery driving signal is output from the data backup power supply due to a power-off operation, or a command word is generated in accordance with performing a scheduled program. The host unit backs up the current operational environment and data in the auxiliary memory storage unit according to the hibernation signal, and outputs a powerdown command word so that the power management system interrupts the system power supply by outputting a main power cut-off signal or outputting a battery power cut-off signal according to the powerdown command word. The power management system resumes the power supply by outputting a power supply signal when a WAKE-UP signal in generated while the power is interrupted. When power is resumed, the host unit retrieves the backed up data and the work environment, identifies the source outputting the WAKE-UP signal, and then performs the corresponding operation.

Computer hibernation system for transmitting data and command words

A method and device for controlling a CPU stop clock interrupt of a computer system. The device includes an idle detector and a control processor. A CPU having a stop clock interrupt mode receives a stop clock interrupt signal and initiates and terminates the stop clock interrupt mode according to a logic state of the stop clock interrupt signal. The control processor receives a signal representing an idle condition of the computer system from the idle detector, an alternate signal for idle detector control of the CPU stop clock interrupt mode, and a control signal for forcing the CPU to resume a normal mode by clearing the stop clock interrupt mode. The idle condition can be defined by a computer user according to a selection of predetermined times during which no user inputs are received by the computer system. The method includes monitoring the idle condition signal, monitoring the alternate signal for idle detector control of the stop clock interrupt mode and monitoring the control signal for forcing the CPU to resume a normal mode by clearing the stop clock interrupt mode. The stop clock interrupt signal is output having a logic state corresponding to the logic combination of the monitored signals.

System for controlling stop clock interrupt mode according to user

A peripheral device input-initiated resume system for a combined hibernation system and back-up power supply for a computer comprises a keyboard controller for inputting an appropriate signal to the operating condition based on the key selected by a user, a power management system for outputting a wake-up signal if the signal is inputted from the keyboard or other input devices, a data back-up power unit for supplying DC voltage in case the power is cut-off suddenly or a user does not use the computer for a predetermined time, a power supplying unit in which a switching-mode power supply SMPS converts the external source AC power at line voltage into DC power at a desired voltage and supplies that power to each device on the main board of the computer, thereby retrieving the previous work again by cutting off power of all devices, once the power is off or when a user does not use the computer for a predetermined time, and supplying the additional power only to the MICOM(Micro Computer) or keyboard controller in the state that a hibernation mode is performed. Then the system repeats supplying power if a signal is input again by a user, and consequently helps a user to use the computer more easily with this hibernation state by retrieving the work to the previous state.

Peripheral device input-initiated resume system for combined hibernation

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Suwon, South Korea

Shung-hyun Cho