Yangtze Memory Technologies Co., Ltd.

Shunfu Chen

Wei Liu

Cheng Gan

Liang Chen

Shi Qi Huang

Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.

Structure and method for forming capacitors for a three-dimensional NAND

Local word line driver device, memory device, and fabrication method are provided. A local word line driver device includes a substrate and an array of transistor structures formed on the substrate. The transistor structures are configured in rows and columns. The substrate includes a plurality of first field regions each between adjacent rows of the transistor structures, and a plurality of second field regions each between adjacent columns of the transistor structures. A deep trench isolation structure is formed in at least one field region of: the plurality of first field regions or the plurality of second field regions, of the substrate.

Local word line driver device, memory device, and fabrication method thereof

A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a plurality of semiconductor device arrays and forming a first interconnect layer on the plurality of semiconductor device arrays. The method also includes forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method further includes bonding the first and second interconnect layers and forming one or more isolation trenches through a second side of the first substrate that is opposite to the first side to expose a portion of the first side of the first substrate. The one or more isolation trenches are formed between first and second semiconductor device arrays of the plurality of semiconductor devices arrays. The method further includes disposing an isolation material to form one or more isolation structures respectively in the one or more isolation trenches.

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Hubei, China

Shunfu Chen