Taiwan Semiconductor Manufacturing Comp. Ltd.

Shun Wu Lin

Matt Yeh

Kuo-Bin Huang

Ming-Hsi Yeh

Chi-Chun Chen

Jian-Jou Lian

Neng-Jye Yang

Ryan Chia-Jen Chen

Chien-Hao Chen

Li-Min Chen

Hui OuYang

Donald Y Chao

Yi-Hsing Chen

Shih-Chang Chen

Yu-Wen Wang

Fang Wen Tsai

Kuo Bin Huang

Fan-Yi Hsu

Ren-Kai Chen

Li-Chen Lee

Shih Min Chang

Tze-Liang Lee

Chi-Ming Yang

Pang-Yen Tsai

Shu-Yuan Ku

Kuang-Yuan Hsu

Peng-Soon Lim

Chung-Ming Wang

Chyi-Shyuan Chern

Chun-Chih Cheng

Zin-Chang Wei

Chih-Chien Chang

Li-Shiun Chen

Chia-Ling Chung

Ouyang Hui

Jim Cy Huang

Ming-Jun Wang

An etchant for etching a cobalt-containing member in a semiconductor structure includes a fluorine-free acid and an alkaline solution, a rate of etching a cobalt-containing member by the etchant is greater than a rate of etching a nitride-containing member by the etchant, and a level of dissolved oxygen of the etchant is less than or equal to 100 ppb. A semiconductor structure, includes a plurality of epitaxial structures over a substrate, a gate structure over the substrate and between two of the plurality of epitaxial structures; a cobalt-containing member over one of the epitaxial structures and adjacent to the gate structure; and a dielectric member over the cobalt-containing member, wherein a top surface of the cobalt-containing member is formed by etching a portion of the cobalt-containing member using an etchant including a fluorine-free acid and an alkaline solution.

Etchant for etching a cobalt-containing member in a semiconductor structure and method of etching a cobalt-containing member in a semiconductor structure

A method of fabricating a semiconductor device is described. A substrate is provided. A first semiconductor region of a first semiconductor material is formed over the substrate and adjacent a second semiconductor region of a second semiconductor material. The first and second semiconductor regions are crystalline. An etchant is selective to etch the first semiconductor region over the second semiconductor region. The entire first semiconductor region is implanted to form an amorphized semiconductor region. The amorphized semiconductor region is etched with the etchant using the second semiconductor region as a mask to remove the amorphized semiconductor region without removing the second semiconductor region.

Semiconductor devices and methods of manufacturing thereof

An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.

Semiconductor device and method of manufacture

A method of etching a cobalt-containing member in a semiconductor structure includes providing an etchant including a fluorine-free acid and an alkaline solution having a pH value between 8.5 and 13, and etching the cobalt-containing member in the semiconductor structure using the etchant, wherein a rate of etching the cobalt-containing member by the etchant is substantially greater than a rate of etching a nitride-containing member by the etchant. An etchant for etching a cobalt-containing member in a semiconductor structure includes a fluorine-free acid, and an alkaline solution having a pH value between 8.5 and 13; wherein a rate of etching a cobalt-containing member by the etchant is substantially greater than a rate of etching a nitride-containing member by the etchant, and a level of dissolved oxygen of the etchant is substantially less than or equal to 100 ppb.

For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.

Wet etch chemistry for selective silicon etch

Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

Method of patterning a metal gate of semiconductor device

A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.

Method for removing dummy poly in a gate last process

A method for cleaning a diffusion barrier over a gate dielectric of a metal-gate transistor over a substrate is provided. The method includes cleaning the diffusion barrier with a first solution including at least one surfactant. The amount of the surfactant of the first solution is about a critical micelle concentration (CMC) or more. The diffusion barrier is cleaned with a second solution. The second solution has a physical force to remove particles over the diffusion barrier. The second solution is substantially free from interacting with the diffusion barrier.

Methods for forming metal gate transistors

A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.

Method of fabricating gate electrode using a treated hard mask

A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.

Method of controlling gate thickness in forming FinFET devices

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Taichung, Taiwan

Shun Wu Lin