Apple Inc.

Shun Wai Go

Timothy John Millet

Jerome Francis Duluk, Jr

Joseph P Bratt

Richard E Hessel

Jack Benkual

Suk Hwan Lim

D Amnon Silverstein

Ting Chen

Bin Ni

Sushma Shrikant Trivedi

Tuan Anh Nguyen

Vaughn Todd Arnold

Stephen L Dodgen

Jason Rupert Redgrave

Emerson S Fang

Abbas Rashid

Sidong Li

Hengwei Hsu

Matthew N Papakipos

Nathan D Tuck

Sam Ng

George Cuan

Abraham Mammen

Bo Hong

Zhaoyu Gong

Joseph P Grass

Lindy Fung

Albert Suan-Wei Tsay

Guy Cote

Thomas Y Ho

Sukalpa Biswas

Jeffrey E Frederiksen

Marc A Schaub

Joseph J Cheng

Thomas Y Yo

In an embodiment, an electronic device may be configured to capture still frames during video capture but may capture the still frames in the 4&#xd7;3 aspect ratio and at higher resolution than the 16&#xd7;9 aspect ratio video frames. The device may interleave high resolution, 4&#xd7;3 frames and lower resolution 16&#xd7;9 frames in the video sequence, and may capture the nearest higher resolution, 4&#xd7;3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16&#xd7;9 frames in the video sequence, and then expand to 4&#xd7;3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16&#xd7;9 video frames responsive to a release of the shutter button.

Modeless video and still frame capture

A context switching method for video encoders that enables higher priority video streams to interrupt lower priority video streams. A high priority frame may be received for processing while another frame is being processed. The pipeline may be signaled to perform a context stop for the current frame. The pipeline stops processing the current frame at an appropriate place, and propagates the stop through the stages of the pipeline and to a transcoder through DMA. The stopping location is recorded. The video encoder may then process the higher-priority frame. When done, a context restart is performed and the pipeline resumes processing the lower-priority frame beginning at the recorded location. The transcoder may process data for the interrupted frame while the higher-priority frame is being processed in the pipeline, and similarly the pipeline may begin processing the lower-priority frame after the context restart while the transcoder completes processing the higher-priority frame.

Video encoder with context switching

In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4&#xd7;3 aspect ratio and at higher resolution than the 16&#xd7;9 aspect ratio video frames. The device may interleave high resolution, 4&#xd7;3 frames and lower resolution 16&#xd7;9 frames in the video sequence, and may capture the nearest higher resolution, 4&#xd7;3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16&#xd7;9 frames in the video sequence, and then expand to 4&#xd7;3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16&#xd7;9 video frames responsive to a release of the shutter button.

Modeless video and still frame capture using interleaved frames of video and still resolutions

Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.

Dual image sensor image processing system and method

In an embodiment, a model may be created using a register-transfer level (RTL) representation (or other cycle-accurate representation) of the controller and the circuitry in the communication fabric to the controller. The request sources may be replaced by transactors, which may generate transactions to test the performance of the fabric and controller. Accordingly, only the designs of the controller and the fabric circuitry may be needed to model performance in this embodiment. In an embodiment, at least some of the transactors may be behavioral transactors that attempt to mimic the operation of corresponding request sources. Other transactors may be statistical distributions, in some embodiments. In an embodiment, the transactors may include a transaction generator (e.g. behavioral or statistical) and a protocol translator configured to convert generated transactions to the communication protocol in use at the point that the transactor is connected to the fabric.

Controller and fabric performance testing

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Deferred shading graphics pipeline processor having advanced features

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.

Graphics processor with pipeline state storage and retrieval

An apparatus and methods for rendering 3D-graphics images preferably includes a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a geometry-operations pipeline, coupled to the port and to the output, the geometry-operations pipeline including a block for performing transformations. In one embodiment, the block for performing transformations includes a co-extensive logical and first physical stages, as well as a second physical stage including multiple logical stages. The second physical stage includes multiple logical stages that interleave their execution.

Apparatus and method for geometry operations in a 3D-graphics pipeline

A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.

Growing community of inventors

Cupertino, CA, United States of America

Shun Wai Go