Taiwan Semiconductor Manufacturing Comp. Ltd.

Shun-Shing Yang

Chun-Chang Chen

Feng-Jia Shiu

Ching-Sen Kuo

Chihy-Yuan Cheng

Chun-Chang Wu

Yong-Shiuan Tsair

Hua-Tai Lin

Po-Wei Liu

Wen-Tuo Huang

Hung-Ling Shih

Tsun-Kai Tsao

Chin-Min Huang

Chia-Cheng Chang

Bo-Han Chen

Lun-Wen Yeh

Chien Wen Lai

Cherng-Shyan Tsay

Sz-Fan Chen

Wei-Lin Chang

Hung-Chang Hsieh

Wang-Pen Mo

S K Yang

Shih-Chi Fu

Chien-Wen Lai

ShihKuang Yang

Chuan-Ling Wu

Sk Yang

Chern-Shyan Tsay

A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

Semiconductor device and manufacturing method thereof

Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

Method and apparatus for integrated circuit mask patterning

A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

Improving surface topography by forming spacer-like components

Surface topography by forming spacer-like components

A semiconductor structure includes a substrate having a first region and a second region being adjacent each other; a first patterned layer formed on the substrate, wherein the first patterned layer includes first features in the first region, wherein the second region is free of the patterned layer; and a first guard ring disposed in the second region and surrounding the first features, wherein the first guard ring includes a first width Wand is spaced a first distance Dfrom the first features, Wbeing greater than D

Integrated circuit structure with guard ring

A method includes forming a patterned layer on a substrate having a first region and a second region being adjacent each other. The patterned layer includes first features in the first region. The second region is free of the patterned layer. The method further includes forming a material layer on the patterned layer and the substrate; forming a first guard ring disposed in the second region and surrounding the first features; forming a flowable-material (FM) layer over the material layer; forming a patterned resist layer over the FM layer, wherein the patterned resist layer includes a plurality of openings; and transferring the plurality of openings to the material layer.

Method of planarizating film

Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate having two different topography areas adjacent to each other. A step-forming material (SFM) is deposited over the substrate. A patterned SFM is formed in the low topography area of the two areas. The formation of the patterned SFM provides a fairly planar surface across over the substrate.

Method of semiconductor integrated circuit fabrication

Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less.

Semiconductor devices and manufacturing methods thereof

Growing community of inventors

Tainan, Taiwan

Shun-Shing Yang