Hitachi, Ltd.

Hitachi Computer Engineering Co., Ltd.

Shun Kawabe

Tomoo Aoyama

Shigeo Nagashima

Noboru Masuda

Masamori Kashiyama

Yoshio Miki

Hiroshi Murayama

Masami Usami

Chikahiko Izumi

Yasuhiko Hatakeyama

Hiroo Miyadera

Hisashi Horikoshi

Koichi Ishii

Yasunori Ushiro

Toshihiko Odaka

Kouichiro Omoda

A logic circuit for use as a selector having multiple inputs and high operation speed. The logic circuit includes a first FET having a first electrode connected to a first power supply, a second electrode connected to an output terminal and a third electrode connected to an intermediate control node, and a plurality of logic blocks parallelly connected between the second power supply and the output terminal. Each logic block includes second and third FETs being of a conductivity type opposite to that of the first FET and connected in series between the output terminal and a second power supply. Each logic block also includes a fourth FET being of the same conductivity type as the second and third FETs and having a third electrode connected to the third electrode of the second FET, a first electrode connected to the third electrode of the third FET and a second electrode connected to the intermediate control node. The conduction resistance between the output terminal and the first power supply is reduced and the parasitic capacitance added to the output terminal is also reduced, thereby allowing the logic circuit to be operated at high speed.

Logic circuit

Vector registers having logically equal address are arranged as two banks which can independently access ultra high speed RAM's. One bank holds all even-numbered elements of vector data and the other bank holds all odd-numbered elements of the vector data. A write address generator and a read address generator which are one half as fast as a clock rate of a machine cycle and which have a phase difference of one half period therebetween are provided so that the clock rate of the machine cycle may be set to one half of a total time of a write pitch and a read pitch of the vector registers.

Vector processor performing data operations in one half of a total time

A method and apparatus for extending an address space for a vector processor including a vector processing unit and a scalar processing unit. A main storage and an extended storage are also disclosed. An address translator is provided for each requestor within the vector processing unit. Each address translator includes registers for storing main storage addresses and extended storage addresses for the address translation, a register for storing information such as an invalid bit regarding an address space present on the main storage, a register for storing information such as a protection bit representative of an address translation enabled area, and registers for storing a reference bit and a write bit representative of the main storage reference status. The scalar processing unit includes an access controller for allowing a write/pad operation relative to the respective registers in the address translator. The vector processing unit includes a first logic circuit for temporarily suspending a main storage reference request sent from the requestor to an area not present on the main storage, a second logic circuit for releasing the suspension, and a third logic circuit for informing the scalar processing unit of the suspension of the main storage reference request.

Method and system for extending address space for vector processing

A vector processor has a plurality of vector processing units each of which is connected to main storage via a plurality of memory port logic units. Each of the vector processing units has a resource management circuit, thereby managing its resources and the plurality of memory port logic units as resources and reporting information of the memory port logic unit determined to be used to other vector processing units. The plurality of memory port logic units are thus shared by the plurality of vector processing units.

Vector processing system for processing plural vector instruction streams

An information processing apparatus having an address translation system includes a plurality of processors in each of which an addressing is carried out by translating a logical address into a real address in the virtual storage system for data processing. The plurality of processors include a scalar processor for translating a logical address into a real address by using an address translation table; and a vector processor for determining if the logical address to be relocated lies within a predetermined address range, for address-relocating the logical address to the real address based on a relocation table when the logical address lies within the predetermined address range, and using the logical address as a real address when the logical address lies outside of the predetermined address range. The predetermined address range and the content of the relocation table are set by the scalar processor which supervises the program storage area.

Address conversion for a multiprocessor system having scalar and vector

An information processing system having a high speed buffer storage and employing an advanced control includes an address stack for storing addresses to be sent to a main storage as readout requests when instruction words or data are not contained in the high speed buffer storage, together with instruction stream numbers and flags for indicating whether the readout requests are conditional requests based on predicted prefetching. For the addresses having the conditional request flags, they are sent as the readout requests when the prediction is finally determined and the other addresses are cancelled. In this manner, the advanced control need not be interrupted.

Apparatus for prefetching instructions

A vector processor provided wtih a vector register to set therein vector element data having been stored in a main storage, prior to a vector operation, is disclosed in which control information indicating whether new element data is read out from the main storage to be set in one location of the vector register capable of storing one vector element data and to be latched, or vector element data having been latched is set in the above location, is set in a mask register, for each location of the vector register, and the control information is successively read out from the mask register, to set vector element data in the vector register in accordance with the read-out control information.

Processor for carrying out vector operation wherein the same vector

A general purpose data processing apparatus is provided which is adapted also for processing vector instructions. An instruction control unit reads instructions out of a memory and decodes them. If the instructions are different from vector instructions, an arithmetic unit performs the instructed operations. If the instructions are vector instructions, the subsequent control is performed by a vector instruction control unit. The vector instruction control unit decodes the vector instructions and controls the vector operands to cause the same arithmetic unit to perform the vector operation in accordance with the vector operands. Thus, the general purpose data processing apparatus can process vector instructions at high speed.

General purpose data processing apparatus for processing vector

A data processing system has a main memory, a buffer memory, an instruction control unit, and an arithmetic unit. The data processing system also includes a register for storing an address for previous transfer and an adder for successively increasing the contents of the register to thereby transfer data in continuous regions of the main memory to the buffer memory when an instruction which causes the arithmetic unit to utilize the data is detected.

Data processing system having a high speed buffer memory

An information processing device for processing instructions, including branch instructions, is characterized in that a route memory is provided for storing branch target addresses of a plurality of branch instructions and branch target instructions in corresponding relationship to the branch target addresses, and the route memory is referenced by the address in a given instruction, whereby the branch target instruction at the corresponding branch target address is read out.

Growing community of inventors

Machida, Japan

Shun Kawabe