Hitachi, Ltd.

Hitachi Computer Engineering Co., Ltd.

Hitachi Computer Electronics Co., Ltd.

Shun Ishiyama

Yoshio Sato

Osamu Tada

Shunsuke Miyamoto

Kaoru Moriwaki

Kazunobu Morimoto

Takao Nishida

Toru Hiyama

Toshifumi Ishii

Satoshi Fujiwara

A design support system for executing logic verification so as to perform work management, progress state management and logic quality management efficiently in a logic verification process and so as to improve the man-hour for development and the throughput of computer resources. For every verification item to be executed, management information including a verification item number for identifying a verification item, confirmation information for indicating the fact that no failure has been confirmed in the verification item, a prerequisite verification item number for identifying another verification item required to be confirmed as a prerequisite for the verification item is stored in a memory of the system. Before execution of logic simulation which is performed by giving test data for logic verification of the design data to the design data as a subject of logic verification, data in the memory are searched so that logic simulation is executed in the case where all verification items as prerequisites for verification items to be executed have been already confirmed.

Design support system and method therefor

In a logic circuit which is logically divided into partial circuits each consisting of a logic block, data holding stages on the input and output sides therof, and a scan circuit segment associated with them, diagnostic data for a logic circuit section is obtained using the scan circuit segments in the respective partial circuits and wherein, only the scan circuit segments in the respective partial circuits are actuated to set values in the output side data holding stages and to read out the contents thereof as diagnostic test data for a scan circuit section.

Diagnosing method for logic circuits

A logic circuit having a diagnostic function is disclosed in which each of first latches for applying data to combinational circuits included in the logic circuit and/or receiving data from the combinational circuits is provided with a second latch and a selector for selecting the output of the first latch in a first mode and for selecting the output of the second latch in a second mode. In a regular operation, the output of the first latch is never transferred through the second latch, and the selector is operated in the first mode. Accordingly, the output of the first latch is supplied directly to a succeeding combinational circuit, and thus the delay caused by the second latch in the prior art can be eliminated. Although the delay caused by the selector is unavoidable, this delay can be made far smaller than the delay caused by the second latch. In a diagnostic operation, the output of the first latch is transferred through the second latch, and the selector is operated in the second mode, in order to perform the diagnostic operation stably even when data is transferred between first latches having the same phase, or the logic circuit includes a one-latch loop.

Logic circuit having a test data scan circuit

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Hadano, Japan

Shun Ishiyama