Csmc Technologies Fab2 Co., Ltd.

Shuming Guo

Hao Wang

Youhui Li

Nan Zhang

Bin Chen

Ming Gu

Jing Zhou

Yong Huang

Zongchuan Wang

Cheng Zhou

Guoyi Zong

Zhijin Li

Maoqian Zhu

Yongqiang Hu

Zhan Gao

Lin Wu

Xinmiao Zhao

A semiconductor memory comprising: a comparison readout circuit comprising a first port configured to receive an electric signal of a read memory unit and a second port configured to receive a reference electric signal, the comparison readout circuit being configured to compare the electric signal of the read memory unit with the reference electric signal to obtain storage information of the memory unit; and a first/second column decoder connected to a first/second memory array and the comparison readout circuit and configured to select a bitline corresponding to the read memory unit when a memory array selection signal enables the first/second memory array, and output the electric signal of the memory unit to the first port by means of the bitline, and further configured to connect a first bitline of the first/second memory array to the second port when the memory array selection signal does not enable the first/second memory array.

Semiconductor memory including a current comparison readout circuit

A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is '0'; and clamping the output end at a clamping voltage when the first signal is “1”.

Semiconductor memory

The present application relates to a resistance simulation method for a power device, comprising: establishing an equivalent resistance model of a power device, wherein the connection relationship of N fingers is equivalent to N resistors Rconnected in parallel, input ends of adjacent resistors Rare connected by means of a resistor R, output ends of adjacent resistors Rare connected by means of a resistor R, and R=R*N+R+R, wherein Rand Rare respectively resistances of a source metal strip and a drain metal strip, Ris a metal resistor of a first intermediate layer connecting one source region to the source metal strip, Ris a metal resistor of a second intermediate layer connecting one drain region to the drain metal strip, and Ris the channel resistance of the power device; and calculating the resistance of the equivalent resistance model as the resistance of the power device.

Power device and resistance simulation method therefor, and power device simulation tool

A readout circuit with a self-detection circuit and a control method therefor. The circuit comprises a pre-charging circuit and a control circuit, the pre-charging circuit and the control circuit being connected to a first node and used for charging a memory unit. The readout circuit also comprises a detection circuit, the detection circuit and the pre-charging circuit being connected to the first node. The detection circuit comprises a third NOT gate, a fourth NOT gate, a first NAND gate, a sixth NOT gate, a first trigger and an eighth NOT gate. In such a manner of detecting the reversal of the first NOT gate through the reversal of the third NOT gate, the charging duration of the first node (A) can be greatly reduced, thereby reducing the reading duration of the whole circuit. At the same time, the re-occurrence of a state of charging the circuit can be avoided after pre-charging has ended.

Readout circuit with self-detection circuit and control method therefor

A method of producing a Macro Read Only Memory (MROM) memory based on a One Time Programmable (OTP) memory is provided. The method includes: removing a floating gate of a second P-type Metal Oxide Semiconductor (PMOS) transistor of an OTP memory cell for storing data '0' in an OTP memory map, such that the OTP memory cell being transferred to a MROM memory cell for storing data '0', and retaining an original structure of the OTP memory cell for storing data &#x201c;1&#x201d; in the OTP memory map, such that the original structure being used as a MROM memory cell for storing data &#x201c;1&#x201d;, thus forming a MROM memory map; and producing a MROM memory according to a MROM memory map. The OTP memory map is debugged to determine data which can be changed into the MROM memory map, and an OTP process can be transferred into a MROM process by adjusting only one mask during a producing process.

Method for producing MROM memory based on OTP memory

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Wuxi, China

Shuming Guo