Changxin Memory Technologies, Inc.

Shuliang Ning

Zhan Ying

Jun He

Jie Liu

The present invention provides a semiconductor device comprising a storage chip and a temperature detection module for detecting a temperature of the storage chip. When the temperature detected by the temperature detection module reaches a set threshold, the storage chip is activated. The present invention utilizes the temperature detection module to detect the temperature of the storage chip so as to provide a reference for the activation and operation of the storage chip, avoiding the activation and operation of the storage chip under low temperatures, shortening write time, and improving the stability of the storage chip write; the temperature detection module has a simple circuit structure and is easy for implementation, with a small occupied area, exerting no influence on the active area of the storage chip.

Semiconductor device

A read/write method includes: applying a read command to a memory device, the read command pointing to address information, reading to-be-read data from a storage cell corresponding to the address information to which the read command points, and if an error occurs in the to-be-read data, storing the address information to which the read command points in a preset storage space. The read/write operation is not performed on the address information stored in the preset storage space when the user executes the read or write operation on the memory device, which avoids a data error or data loss and greatly improves the reliability and prolongs the service life of the memory device.

Read/write method and memory device

The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and storing the address information pointed to by the read command into a preset memory space if an error occurs in the data to be read out, and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule.

Method for reading and writing and memory device

The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, and each of the plurality of memory bits is associated with a spare memory cell.

The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and setting a mark of the address information pointed to by the read command as invalid if an error occurs in the data to be read out, and backing up the address information pointed to by the read command and the mark into a non-volatile memory cell according to a preset rule.

A read and write method includes: applying a read command to a memory device, the read command indicating address information; reading data to be read from a storage unit corresponding to the address information indicated by the read command; and if an error occurs in the data to be read, associating the address information indicated by the read command with a spare storage unit, and backing up the address information indicated by the read command and association information between the address information and the spare storage unit in a non-volatile storage unit based on a preset rule.

Read and write methods and memory devices

A read/write method and a memory are provided. The read/write method includes: issuing a read command to a memory, wherein the read command points to an address; reading to-be-read data from a storage unit corresponding to the address to which the read command points; and in response to an error occurring in the to-be-read data, marking the address to which the read command points as disabled. When executing a read/write operation on the memory, the address of the storage unit is marked to distinguish an enabled storage unit from a failed storage unit in real time. A data error or a data loss can be avoided, thereby greatly improving the reliability and the service life of the memory.

Systems and methods for read/write of memory devices and error correction

The embodiments provide a method for reading and writing and a memory device. The method for reading and writing includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and associating the address information pointed to by the read command with a spare memory cell if an error occurs in the data to be read out. The method for reading and writing provided by the present disclosure greatly improves reliability of the memory device and prolongs lifespan of the memory device.

A semiconductor memory is provided. The semiconductor memory comprises a memory chip and a voltage regulation unit. The memory chip includes at least a storage array and the voltage regulation unit includes at least an operational amplifier. The voltage regulation unit is configured to convert an external input first voltage into a second voltage to be provided to a word line driver circuit associated with the memory chip. The first voltage is greater than the second voltage. According to the semiconductor memory provided, power consumption of the memory chip (or the semiconductor memory) is reduced and the second voltage provided to the word line driver circuit reaches a threshold voltage.

Semiconductor memory

A semiconductor structure and a preheating method thereof are provided. The semiconductor structure includes: a storage chip; a temperature detection unit configured to detect a temperature of the storage chip before the storage chip initiates; and a control chip configured to: before the storage chip initiates, heat the storage chip and determine whether the temperature detected by the temperature detection unit reaches a specified threshold; and if the temperature reaches the specified threshold, control the storage chip to initiate. When the semiconductor structure provided in the present invention works at a low temperature, the storage chip may be heated to the specified threshold, thereby preventing an increase of the resistances on the bit line, the word line, and the metal connection line in the storage chip, and improving the performance of read/write operations of the memory.

Semiconductor structure and preheating method thereof

The present application provides a storage system including a data port. The data port includes a data output unit. The data output unit includes: a pull-up unit having a control terminal, a first terminal and a second terminal, a first input signal being inputted to the control terminal, the first terminal being electrically connected to a power supply, the second terminal being connected to an output terminal of the data output unit, and the pull-up unit being a first NMOS transistor; and a pull-down unit having a control terminal, a first terminal and a second terminal, a second input signal being inputted to the control terminal, the first terminal being electrically connected to a ground terminal, and the second terminal being connected to the output terminal of the data output unit.

Storage system

The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, each of the plurality of memory bits being associated with a spare memory cell; and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule.

A semiconductor device is provided, which includes a memory chip and a temperature detection module. The temperature detection module is configured to detect a temperature of the memory chip. The temperature detection module includes a temperature detection unit. The temperature detection unit includes a temperature sensitive unit and an adjustable resistor unit. An electrical conductivity of the temperature sensitive unit changes with the change of temperature, and the adjustable resistor unit being connected in parallel with the temperature sensitive unit. The temperature detection unit is configured to be calibrated by adjusting a resistance value of the adjustable resistor unit.

A semiconductor device is provided, including a plurality of memory chips and a temperature detection module. The temperature detection module includes: a plurality of temperature detection units, in which the plurality of temperature detection units are disposed on at least part of the memory chips to detect the temperatures of at least part of the memory chips; and a processing unit, in which the plurality of temperature detection units share the processing unit with each other, and the processing unit is configured to process a signal of at least one of the temperature detection units.

A semiconductor device is provided, including multiple memory chips and a temperature detection module. The temperature detection circuit includes: multiple temperature sensitive units, arranged on the memory chips to detect temperatures of the memory chips; and a processing unit. The multiple temperature sensitive units share the processing unit with each other. The processing unit is configured to process a signal of at least one of the temperature sensitive units. The processing unit includes a calibration value memory cell and a calibration unit. The calibration value memory cell is configured to store a calibration value corresponding to the temperature sensitive unit. The calibration unit is configured to calibrate the temperature sensitive unit according to the calibration value.

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Hefei, China

Shuliang Ning