Fujitsu Corporation

Shuji Yamamura

Takashi Aoki

Kouichi Kumon

Toshio Yoshida

Kazuhiro Matsumoto

Masahiro Kuramoto

Takumi Maruyama

Masato Nakagawa

Miyuki Ono

Atsushi Mori

Iwao Yamazaki

Go Sugizaki

Naohiro Kiyota

Ryuji Kan

Tsuyoshi Motokurumada

Mikio Hondou

Toru Hikichi

Akira Hirai

Takashi Toyoshima

Koichi Onodera

Mikio Hondo

Masaharu Maruyama

Yoshimasa Tani

Makoto Komagata

Tani Yoshimasa

A processor includes: an address generating unit that, when an instruction decoded by a decoding unit is an instruction to execute arithmetic processing on a plurality of operand sets each including a plurality of operands that are objects of the arithmetic processing, in parallel a plurality of times, generates an address set corresponding to each of the operand sets of the arithmetic processing for each time, based on a certain address displacement with respect to the plurality of operands included in each of the operand sets; a plurality of instruction queues that hold the generated address sets corresponding to the respective operand sets, in correspondence to respective processing units; and a plurality of processing units that perform the arithmetic processing in parallel on the operand sets obtained based on the respective address sets outputted by the plurality of instruction queues.

Processor and control method of processor for address generating and address displacement

A plurality of floating-point registers store data therein. A processing execution unit executes arithmetic processing by using data stored in the floating-point registers. A first switch and a second switch select a route connecting the processing execution unit and the floating-point registers. A switch control unit controls the first switch and the second switch so as to switch a route to be selected, based on a switching instruction from the processing execution unit.

Arithmetic processing device and control method for arithmetic processing device

A processor includes an arithmetic processing circuit, a cache memory including a plurality of ways, a usage information register storing usage information indicating whether to use each of the plurality of ways, a purge control circuit performing purge processing on a basis of rewriting of the usage information within the usage information register according to an instruction executed by the arithmetic processing circuit, the purge processing including processing of deleting, from the cache memory, target data retained in a target way to be stopped and processing of writing back part of the target data, the part of the target data being data rewritten in the cache memory, to a main memory at a lower level than the cache memory, and an access control circuit controlling accessing the cache memory on a basis of a memory access request received from the arithmetic processing circuit and status of the purge processing.

Processor and method

An arithmetic processing apparatus includes a prefetch unit configured to send a prefetch request to a subordinate cache memory for prefetching data of a main storage device into a primary cache memory. The arithmetic processing apparatus further includes a count unit configured to count a hit count of how many times it is detected that prefetch request target data is retained in the subordinate cache memory when executing a response process to respond to the prefetch request sent from the prefetch unit. The arithmetic processing apparatus yet further includes an inhibition unit configured to inhibit the prefetch unit from sending the prefetch request when the counted hit count reaches a threshold value.

Arithmetic processing apparatus and control method of the arithmetic processing apparatus

An arithmetic processing apparatus has OS arithmetic processing unit executing instruction of OS, general-purpose arithmetic processing units each executing an instruction other than OS, a shared cache unit including a shared cache memory, a cache control unit and a request selection circuit which selects a memory access request from the arithmetic processing units, and a data buffer temporarily storing data of the memory access request, and a memory access control unit controlling a memory access to a main memory. The shared cache unit has a memory access band control register to which either one or both of a first set value, which includes an entry criterion for the request selection circuit to enter the memory access request from OS arithmetic processing unit, and a second set value which sets a capacity of a storage area in the data buffer for storing the data are set.

Arithmetic processing apparatus and control method therefor

An arithmetic processing device has a first arithmetic processing unit including a first instruction controller that controls a write instruction to a memory and a first cache unit, and a second arithmetic processing unit including a second instruction controller and a second cache unit. The first arithmetic processing unit transmits an invalidation request to the second arithmetic processing unit when a write request to the memory is issued within a first transaction, and in response to the invalidation request, the second cache unit determines whether a second transaction is to be aborted based on information in the invalidation request when the second transaction conflicts with the first transaction for a cache block corresponding to a destination of the write request, and sends a determination result to the first arithmetic processing unit.

Arithmetic processing device, method of controlling arithmetic processing device, and information processing device

A computational processing device includes: a computational-processor that outputs access requests to a storage device; a plurality of request-holding-units that respectively hold access requests output by the computational processor according to individual access types, the access types being types of access requests; an arbitration-unit that arbitrates access requests held in the plurality of request holding units; a buffer-unit that includes a plurality of entries that hold data; and a buffer-controller that causes one of the plurality of entries to hold data output by the storage device in response to an access request arbitrated by the arbitration unit, on the basis of a result of comparing, for each access type, a count value that counts, for each access type, the number of entries holding data from among the plurality of entries against a maximum value for the number of entries made to hold data for each access type.

Computational processing device including request holding units each provided for each type of commands, information processing device including request holding units each provided for each type of commands, and method of controlling information processing device

An arithmetic processing device having an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation, and a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction relating to the memory allocation area.

Arithmetic processing device, information processing device, control method for information processing device, and control program for information processing device

In an accounting apparatus, a conflict determination unit determines whether or not the accounting mode is in a conflict state where a process is executing in another logical CPU and stores the determination result in an accounting information storage unit, when a process of the user starts to be executed in a logical CPU of an SMT processor. And a CPU use time acquisition unit collects the CPU use time of the process in the conflict state or the non-conflict state distinctively and stores it in an accounting information storage unit. Thereafter, a CPU use time conversion unit converts the CPU use time in the conflict state, with a predetermined weighting, based on the CPU use time in the conflict state and the non-conflict state, after the end of executing the process, and an accounting calculation unit calculates the accounting amount for the process from an effective use time.

Accounting apparatus and method for SMT processor

An information processing system performs a prefetch for predicting data that is likely to be accessed by a central processing unit, reading the predicted data from a main memory, and storing the data in a cache area in advance. The information processing system includes a usage information storage unit that stores therein usage information indicating whether prefetched data has been accessed; and a usage information writing unit that writes the usage information of the prefetched data in the usage information storage unit.

Information processing system and information processing method

A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.

Cache memory having sector function

A prefetch processing apparatus includes a central-processing-unit monitor unit that monitors processing states of the central processing unit in association with time elapsed from start time of executing a program. A cache-miss-data address obtaining unit obtains cache-miss-data addresses in association with the time elapsed from the start time of executing the program, and a cycle determining unit determines a cycle of time required for executing the program. An identifying unit identifies a prefetch position in a cycle in which a prefetch-target address is to be prefetched by associating the cycle determined by the cycle determining unit with the cache-miss data addresses obtained by the cache-miss-data address obtaining unit. The prefetch-target address is an address of data on which prefetch processing is to be performed.

Prefetch processing apparatus, prefetch processing method, storage medium storing prefetch processing program

The execution status of pipeline processing is highly visualized by appropriately displaying processes forming loops in a simplified manner. A loop-information storage unit stores loop-defining information specifying the address of an instruction that causes a pipeline process forming a loop. An operation-information storage unit stores operation information that includes the address of an instruction input into a pipeline and information indicating the execution status of a pipeline process caused by the instruction. A loop determination unit determines whether each pipeline process indicated by the operation information forms a loop by referring to the loop-defining information. An output unit outputs visualization information indicating, in a visually comprehensible manner, the execution status of a pipeline process that has been determined to form a loop for a predetermined number of executions of the loop and the execution status of a pipeline process that has been determined to form no loop.

Storage medium storing calculation processing visualization program, calculation processing visualization apparatus, and calculation processing visualization method

A communication performance analyzing program, a communication performance analyzing apparatus and a communication performance analyzing method make it possible to highly reliably grasp the communication performance of a computer system by automatically analyzing the communication performance. The communication performance analyzing program that causes a computer to analyze a data tendency of communication performance of a plurality of execution periods of a computer system formed by connecting a plurality of computers by a network, the program comprises a communication time acquisition step Sthat acquires communication time data among the computers of the computer system and a statistical analysis step Sthat analyzes the tendency of communication performance data of each execution period of the computer system, using the communication time among the computers, by statistically analyzing the communication time data acquired by the communication time acquisition step.

Communication performance analyzing program, communication performance analyzing apparatus and communication performance analyzing method

The system provides a technique for detecting changes in behavior of a computer system. An address data storing unit obtains an address being accessed by a CPU at prescribed sampling intervals, stores address data comprising the address and its acquisition time in an address record table in time series. Then an executed process detector detects the name of the process that was executed when the address data was obtained, and sets the process name for the address data in the address record table. When an analysis request specifying an analysis time period is made, an analyzer counts up each of the process names included in the address data being stored in the address record table for each specified analysis time period, and analyzes the breakdown of executed processes for each analysis time period. Then a display unit displays the analysis result of the analyzer.

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Yokohama, Japan

Shuji Yamamura