Matsushita Electric Industrial Co., Ltd.

Shuji Tsukiyama

Masahiro Fukui

Masakazu Tanaka

Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.

Delay distribution calculation method, circuit evaluation method and false path extraction method

A physical design method optimizes the performance of an integrated circuit much more efficiently. After an initial layout is obtained for an integrated circuit, a set of process steps, including evaluating the overall performance of the integrated circuit, selecting a candidate cell and changing the performance of the cell, is carried out a number of times. In the step of selecting a candidate cell, a cell, which should have its performance changed, is selected from multiple cells included in the integrated circuit based on the performance evaluation result obtained. Then, by reference to a library, a characteristic representing the performance of the candidate cell is determined in accordance with an external condition imposed thereon.

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Tokyo, Japan

Shuji Tsukiyama