Ricoh Company, Ltd.

Micron Technology Incorporated

Fuji Xerox Co., Ltd.

Toshiba Mitsubishi-electric Industrial Systems Corporation

Nissan Kohki Co., Ltd.

Shuji Tanaka

Yoshiaki Fukuzumi

Jun Fujiki

Masanobu Saito

Yoshihiko Kamata

Masashi Yoshida

Yuji Arai

Hiroshi Ono

Toshio Koike

Yoshio Hattori

Ken Amemiya

Takatsugu Fujishiro

Shinichi Kawahara

Hiroyuki Nagashima

Takeo Suda

Nobuo Kuwabara

Masahiko Shakuto

Shinji Sato

Yutaka Takahashi

Naohiro Kumagai

Masanori Kawasumi

Takaaki Tawada

Masato Yanagida

Tomoharu Tanaka

Hiroyuki Sugiyama

Yoshinori Nakagawa

Hiroshi Hosokawa

Masami Tomita

Naoki Fujiwara

Ching-Huang Lu

Hiroshi Nakai

Atsushi Kurokawa

Paolo Tessariol

Richard J Hill

Manabu Nonaka

Kazuhisa Sudo

Matthew J King

Kunal Shrotri

Takeshi Kojima

Yoshiyuki Kimura

Shin Kayahara

Ichiro Kadota

Yasunobu Youda

Michiya Okamoto

Keiichi Yoshida

Tokuya Ojimi

Hiroomi Harada

Yasuhiro Kawashima

Takeshi Tabuchi

Teruyuki Kasuga

Takashi Yukutake

Kenji Kameyama

Ryuji Yoshida

Haruji Mizuishi

Shigekazu Enoki

Shinichiro Naruse

Kenji Honjoh

Hajime Nishida

Mikio Ishibashi

Umberto Maria Meotto

Takuzi Yoneda

Taku Kudoh

Sidhartha Gupta

Naoyuki Ozaki

Matsuyuki Aoki

Akihiro Fujita

Eiki Yoshimizu

Takuya Suganuma

Shoji Asanuma

Toshikazu Tsumita

Kazumasa Ishikawa

Yohzoh Dohki

Matthew Holland

Kyle A Ritter

Avinash Rajagiri

Shigeyuki Ito

Chohtaroh Kataoka

Yuji Ishikura

Hiroki Atari

Kye Hyun Baek

Tamotsu Sakamoto

Yoshio Tsuji

Toshiaki Tsuboi

Aman Gupta

Akio Okamura

Kazuo Nakatani

Takahiro Terazono

Hidemasa Sato

Yohzoh c/o Ricoh Elemex Corp Dohki

Shigeyuki c/o Ricoh Elemex Corp Ito

A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.

Fast program recovery with reduced programing disturbance in a memory device

A microelectronic device comprises a stack structure, pillar structures, a conductive plug structure, a sense transistor, and selector transistors. The stack structure comprises a vertically alternating sequence of conductive material and insulative material, and is divided into blocks separated by dielectric slot structures. The blocks individually include sub-blocks horizontally extending in parallel with one another. The pillar structures vertically extend through one of the blocks of the stack structure. Each pillar structure of a group of the pillar structures is positioned within a different one of the sub-blocks of the one of the blocks than each other pillar structure of the group. The conductive plug structure is coupled to multiple of the pillar structures of the group of the pillar structures. The sense transistor is gated by the conductive plug structure. The selector transistors couple the sense transistor to a read source line structure and a digit line structure.

Microelectronic devices, and related memory devices and electronic systems

Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a plurality of sets of field-effect transistors with each of the sets of field-effect transistors between the data line and a respective string of series-connected memory cells and having N field-effect transistors that are fabricated to have a respective binary permutation of two threshold voltages of a plurality of possible binary permutations of two threshold voltages having N positions, and N select lines that are each connected to a control gate of a respective field-effect transistor of each of the sets of field-effect transistors.

Apparatus containing memory array structures having multiple sub-blocks

Methods of forming integrated circuit structures for a capacitive sense NAND memory include forming a first semiconductor overlying a dielectric, forming a second semiconductor to be in contact with a first end of the first semiconductor, forming a third semiconductor to be in contact with a second end of the first semiconductor opposite the first end of the first semiconductor, forming a vertical channel material structure overlying the first semiconductor and having a channel material capacitively coupled to the first semiconductor, and forming a plurality of series-connected field-effect transistors adjacent the vertical channel material structure.

Methods of forming integrated circuit structures for capacitive sense NAND memory

A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

Microelectronic devices including tiered stacks including conductive structures isolated by slot structures, and related electronic systems and methods

Arrays of memory cells might include a first upper data line, a second upper data line, a lower data line, a first pass gate selectively connected to the lower data line, a second pass gate connected to the first pass gate and selectively connected to the lower data line, a third pass gate selectively connected to the lower data line, a fourth pass gate connected to the third pass gate and selectively connected to the lower data line, unit column structures selectively connected to a respective one of the upper data lines and capacitively coupled to a first channel of a respective one of the pass gates, and control lines capacitively coupled to a second channel of a respective one of the pass gates.

Memory array structures for capacitive sense NAND memory

Arrays of memory cells might include a data line, a source, a plurality of pass gates connected in series between the data line and the source, a plurality of unit column structures each having a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of its respective plurality of series-connected field-effect transistors are selectively connected to one another, and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates, wherein, for each unit column structure of the plurality of unit column structures, the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates.

Sense line structures in capacitive sense NAND memory

Memory might include a plurality of series-connected non-volatile memory cells, a plurality of series-connected first field-effect transistors connected in series with the plurality of series-connected non-volatile memory cells, and a second field-effect transistor, wherein the channel of the second field-effect transistor is capacitively coupled to channels of the plurality of series-connected first field-effect transistors. The memory might further include a controller configured to cause the memory to selectively activate a selected non-volatile memory cell, activate each remaining non-volatile memory cell, increase a voltage level of the respective channel of each first field-effect transistor, selectively discharge the voltage level of the respective channel of each first field-effect transistor through the selected non-volatile memory cell, and determine whether the second field-effect transistor is activated in response to a remaining voltage level of the respective channel of each first field-effect transistor.

Access operations in capacitive sense NAND memory

An array of memory cells might include a first data line, a second data line, a source, a capacitance selectively connected to the first data line, a string of series-connected non-volatile memory cells between the first data line and the capacitance, and a pass gate selectively connected between the second data line and the source, wherein an electrode of the capacitance is capacitively coupled to a channel of the pass gate.

Capacitive sense NAND memory

Memory might include a non-volatile memory cell, a capacitance selectively connected to the non-volatile memory cell, a field-effect transistor having a channel capacitively coupled to an electrode of the capacitance, and a controller for access of the non-volatile memory cell configured to cause the memory to increase a voltage level of the electrode of the capacitance, selectively discharge the voltage level of the electrode of the capacitance through the non-volatile memory cell responsive to a data state stored in the non-volatile memory cell, and determine whether the field-effect transistor is activated in response to a remaining voltage level of the electrode of the capacitance.

Arrays of memory cells a plurality of sense lines each having a respective plurality of pass gates connected in series between a second data line and a source, and having a respective subset of unit column structures capacitively coupled to first channels of its respective plurality of pass gates, wherein, for each sense line of the plurality of sense lines, each unit column structure of its respective subset of unit column structures is connected to a respective first data line of a respective subset of first data lines.

Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.

Memory device including multiple gate-induced drain leakage current generator circuits

A photovoltaic system includes power generators configured to generate power utilizing sunlight, inverters configured to convert the power generated by the power generators into alternating-current power output to a power system, a first limiter configured to limit output power of the inverters not more than a predetermined capacity, a second limiter configured to limit output power of at least one of the inverters to a level exceeding the predetermined capacity limited by the first limiter, when a predetermined condition is satisfied, and an inverter controller configured to control the output power of the inverters, based on the first limiter or the second limiter.

Photovoltaic system

The image forming apparatus includes a latent image bearing member; a charging device charging the surface of the latent image bearing member; a latent image forming device forming an electrostatic latent image on the surface of the latent image bearing member; a developing device supplying toner to the electrostatic latent image to form a toner image; a cover film supplying device supplying a cover film to the surface of the latent image bearing member at a cover film supplying position located on an upstream side from the development position so that the toner image is formed on the cover film covering the surface of the latent image bearing member; and a cover film separating device separating the cover film bearing the toner image thereon from the surface of the image bearing member before the cover film bearing the toner image thereon reaches the cover film supplying position.

Electrophotographic image forming method and apparatus with a cover film supplying device

Growing community of inventors

Kanagawa, Japan

Shuji Tanaka