Hitachi, Ltd.

Shuji Sugimoto

Hiroyuki Kurosawa

Kiyoshi Hisano

Kenji Kubota

Ken Hirashima

Hisaharu Takeuchi

Masahiko Sato

Kiyoshi Honda

Yoshiro Shiroyanagi

Norio Hamada

A storage device controlling apparatus connected to a storage device storing data and connected to an information processing apparatus via a network, the apparatus being accommodated in a chassis, the apparatus comprising a circuit board accommodated in the chassis, the circuit board including: an I/O processor formed thereon, the I/O processor outputting to the storage device I/O requests corresponding to requests to input and output data from the information processing apparatus; an inner connector provided at an end to be located on an inner side of the chassis, at least the I/O processor and a power supply unit being connected through the inner connector; a file access processing section formed thereon, the file access processing section accepting the requests to input and output data on a file basis; and an electric power connector provided at an end to be located on an outer side of the chassis, electric power being supplied to the file access processing section through the electric power connector.

Storage device controlling apparatus and a circuit board for the same

The storage subsystem is connected to an external device and comprises a storage device arrangement portion, on which a plurality of storage devices is arranged, and a control device that controls communications between the plurality of storage devices arranged on the storage device arrangement portion and the external device. The storage device arrangement portion is constituted such that the plurality of storage devices is arranged upright in the directions of two dimensions.

Storage subsystem

In a magnetic disk controller equipped with a cache memory for disks, the controller in accordance with the present invention includes high order paths for data transfer between a high order channel apparatus and the cache memory through a certain one of a plurality of channel adaptors, low order paths for data transfer between a low order device, e.g. a magnetic disk device, and the cache memory through a certain one of a plurality of device adaptors and a path for data transfer betweeen the low order device and the channel cevice without passing through the cache memory by selecting empty device adaptor and channel adaptor by the switching operation of a switch. When an interrupt is generated from the device, data transfer can be made easily even when the high order path and the low order path are busy, and path utilization efficiency can be improved.

Controller of paths for data transfer in system having external memory

A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, accesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes. As a result, a cache memory accessible with high speed is obtained, and the utilization efficiency of the data stored in the cache memory is substantially improved, improving the data throughput between the CPU and the DKU.

External memory control techniques with multiprocessors improving the

A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, acesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes. As a result, a cache memory accessible with high speed is obtained, and the utilization efficiency of the data stored in the cache memory is substantially improved, improving the data throughput between the CPU and the DKU.

Growing community of inventors

Kanagawa, Japan

Shuji Sugimoto