Sharp Kabushiki Kaisha Corporation

Sharp Kabsuhiki Kaisha

Shuji Nishi

Yuhichiroh Murakami

Yasushi Sasaki

Shige Furuta

Seijirou Gyouten

Takahiro Yamaguchi

Makoto Yokoyama

Takashi Satoh

Keiichi Ina

Takahiro Sasaki

Sachio Tsujino

Ming Ni

Hiroyuki Adachi

Kazuhiro Maeda

Yohsuke Fujikawa

Tamotsu Sakai

Ichiro Shiraki

Etsuo Yamamoto

Satoshi Fujii

Eiji Matsuda

Yousuke Nakagawa

Masakazu Satoh

Hidekazu Yamanaka

Takuya Hachida

Nami Nagira

Tomoyuki Nagai

A liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, and a plurality of pixels. Each of the pixels has a reflection region for performing display in a reflective mode. The first substrate includes a pixel electrode provided in each of the pixels and a reflection layer positioned opposite to the liquid crystal layer with respect to the pixel electrode. The reflection layer has a first region positioned in each of the pixels and a second region positioned between any two pixels adjacent to each other. Voltages of an identical polarity are applied to the liquid crystal layer for any two pixels adjacent to each other in a row direction, for any two pixels adjacent to each other in a column direction, or for all the pixels.

Liquid crystal display device

A liquid crystal display device includes a first substrate, a second substrate, a vertical alignment liquid crystal layer, and a plurality of pixels. Each of the pixels includes a reflective region for performing display in a reflection mode. The first substrate includes a reflective electrode including a first region located within each of the plurality of pixels and a second region located between any two pixels, of the plurality of pixels, adjacent to each other, a transparent insulating layer provided to cover the reflective electrode, and a pixel electrode formed from a transparent conductive material and provided on the transparent insulating layer in each of the plurality of pixels. The second substrate includes a counter electrode provided to be opposite to the pixel electrode and the reflective electrode. Voltage of the same polarity is applied to the liquid crystal layer of any two pixels, of the plurality of pixels, adjacent to each other along a row direction, any two pixels, of the plurality of pixels, adjacent to each other along a column direction, or all of the plurality of pixels. The counter electrode and the reflective electrode are provided with potentials different from each other.

A liquid crystal display device includes a first substrate, a second substrate, a vertical alignment liquid crystal layer, and a plurality of pixels. Each of the pixels includes a reflective region for performing display in a reflection mode. The first substrate includes a reflective electrode including a first region located within each of the plurality of pixels and a second region located between any two pixels, of the plurality of pixels, adjacent to each other, a transparent insulating layer provided to cover the reflective electrode, and a pixel electrode formed from a transparent conductive material and provided on the transparent insulating layer in each of the plurality of pixels. The second substrate includes a counter electrode. Voltage of the same polarity is applied to the liquid crystal layer of any two pixels, of the plurality of pixels, adjacent to each other along a row direction, any two pixels, of the plurality of pixels, adjacent to each other along a column direction, or all of the plurality of pixels. A time average of voltage applied between the pixel electrode and the reflective electrode is substantially the same between a maximum gray scale display state and a minimum gray scale display state.

Liquid crystal display device wherein a time average of voltage applied between a pixel electrode and a reflective electrode is substantially the same in a maximum and minimum gray scale display state

A display device includes a pixel unit, a binary driver, and a timing generator. The display device is an active matrix display device configured to receive a data signal including image data and other data different from the image data. The pixel unit includes a memory configured to store the image data. The binary driver includes a first holding circuit configured to hold the image data and at least one second holding circuit configured to hold the other data. The timing generator is configured to generate a drive signal used for driving the binary driver.

Display device using binary driver having several holding circuits

A plurality of pieces of serial data are supplied to a liquid crystal display device from an outside. An SI signal selection circuit switches processing target data to be captured between one piece of serial data included in the plurality of pieces of serial data and the plurality of pieces of serial data in accordance with a serial data selection signal. The processing target data captured by the SI signal selection circuit is converted into parallel data by a data conversion circuit. In accordance with one clock pulse of a serial clock, serial-parallel conversion processing is performed in parallel on a plurality pieces of serial data.

A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.

Data signal line drive circuit and liquid crystal display device provided with same

A display device includes a reflective electrode, a driving circuit section, a wiring, and a wiring expansion section. The reflective electrode is divided into split electrodes arranged with spaces, which transmit light, respectively provided thereamong and reflects light. The driving circuit section drives the reflective electrode. The wiring is connected to at least the split electrodes and the driving circuit section and composed of a conductive material having a light transmission property. The wiring expansion section is formed to expand in the wiring to overlap the space.

Display device

A shift register is realized having a simple construction with which it is possible to switch the scanning order of gate bus lines and the occurrence of an erroneous operation caused by a threshold voltage drop can be prevented. Unit circuits that make up the shift register are configured of: a thin film transistor in which a third clock is supplied to the gate terminal, the drain terminal is connected to a first node, and a first input signal (output signal of prior stage) is supplied to the source terminal; a thin film transistor in which a second clock is supplied to the gate terminal, the drain terminal is connected to the first node, and a second input signal (output signal of subsequent stage) is supplied to the source terminal; and a thin film transistor in which the gate terminal is connected to the first node, a first clock is supplied to the drain terminal, and the source terminal is connected to an output terminal. The shift direction is switched by changing the generation order of pulses of clock signals.

Shift register

A shift register is configured by connecting unit circuitsin multiple stages. An output transistor Trswitches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Trswitches between whether or not to provide an output of an on-potential output unitto a gate terminal of Trin accordance with an output of a set control unit. The set control unitcontrols a gate terminal of Trinto a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr. The gate potential of Tris raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.

A shift register is configured by connecting unit circuitsin multiple stages. An output transistor Trswitches between whether or not to output a clock signal CKA in accordance with a gate potential. A drain terminal of an initialization transistor Tra is connected to a gate terminal of the Tr, and a source terminal thereof is connected to an output terminal OUT or a clock terminal CKA. The source terminal of the Tra is connected to a node which has a low-level potential at the time of initialization and has a potential at the same level as the clock signal when the clock signal having a high-level potential is outputted. Thus, at the time of outputting the clock signal having the high-level potential, application of a high voltage between the source and the drain of the Tra is prevented, and degradation and breakdown of the initialization transistor are prevented.

In a region extending along a terminal region located near a substrate end and included in a frame region defined around a rectangular display region, a peripheral circuit section is provided between the display region and a mount region defined in part of the terminal region. The peripheral circuit section includes unit circuit sections that are monolithically provided and are aligned along one side of the display region. The arrangement pitch of outer ones of the unit circuit sections is larger than that of inner ones of the unit circuit sections.

Active matrix substrate and display panel including the same

A memory-type liquid crystal display device includes transistors (N, N), retention electrodes (MRY), refresh output control sections (RS), and capacitors (Cb). In a data retention period, an electric potential of each of the retention electrodes (MRY) is changed via a corresponding one of the capacitors (Cb) by changing an electric potential level of a retention capacitor wire signal that is supplied to a corresponding CS line (CSL(i)). Each of the refresh output control sections (RS) receives the electric potential thus changed of a corresponding one of the retention electrodes (MRY) via the input section and controls an electric potential of a corresponding pixel electrode (PIX) in accordance with the electric potential thus changed.

Liquid crystal display device and method for driving same

In an active matrix display apparatus including: pixels provided in a matrix pattern, the pixels each including a memory circuit which retains data while refreshing the data, a data signal electric potential which is supplied from a source line in a period tand written to a node which is connected to a liquid capacitor is higher than a data electric potential of the node, the data electric potential being obtained in a period tafter a refresh operation of the memory circuit.

Display apparatus and display apparatus driving method

A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.

Memory device and display device equipped with memory device

A transistor (N) has a gate terminal connected to a word line (Xi()) and a first conduction terminal connected to a bit line (Yj). A transistor (N) has a gate terminal connected to the word line (Xi()) and a first conduction terminal connected to a node (PIX). A transistor (N) has a gate terminal connected to a node (MRY) and a first conduction terminal connected to the word line (Xi()). A transistor (N) has a gate terminal connected to the word line (Xi()), a first conduction terminal connected to a second conduction terminal of the transistor (N), and a second conduction terminal connected to the node (PIX). Capacitors (Ca), (Cb), (Cap) are formed between the node (PIX) and a reference electric potential wire (RL), between the node (MRY) and the reference electric potential wire (RL), and between the first conduction terminal of the transistor (N) and the node (MRY), respectively.

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Osaka, Japan

Shuji Nishi