Sanyo Electric Co., Ltd.

Shuji Motegi

Tetsuya Tokunaga

Hiroyuki Arai

Takeshi Kimura

Takeshi Hibino

Toshiyuki Ozawa

An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.

Interface circuit and a clock output method therefor

An interface circuit which outputs a clock signal and data to a data register that serially reads in the data synchronously with the clock signal, in response to a control signal changing from one level to the other level, for outputting the clock signal and the data. The interface circuit comprises a clock output circuit that, responding to the level of the clock signal when the control signal changes from the one level to the other level, outputs clocks of the clock signal that are the same in number as bits of the data to the data register.

A liquid crystal driving integrated circuit capable of adjusting display contrast and requiring no externally attached components. A resistor formed by four serially connected resistor elements R has one end connected to a reference voltage VLCD applied from an operational amplifier and the other end connected to an external variable resistor through a terminal Consequently, liquid crystal driving voltages VLCD VLCD VLCD VLCD and VLCD can be finely adjusted not only by eleven versions of reference voltage VLCD in accordance with voltages at respective connection points of twelve serially connected resistor elements, but by changing the resistance of the external variable resistor to thereby provide a liquid crystal driving integrated circuit that can be used for a variety of general purposes. Since only one external variable resistor is required and this resistor is inherently variable, there is no need to consider variation in characteristics.

Integrated circuit for driving liquid crystal

A liquid crystal driving integrated circuit capable of adjusting display contrast and requiring no externally attached components. Transmission gates TG -TG are provided at respective connection points of twelve resistor elements connected in series between a power supply and the ground. One of the voltages V -V derived from the transmission gates TG -TG in accordance with control signals CA -CA is applied to an operational amplifier and used as a reference voltage VLCD . The control signals CA -CA are obtained by decoding control data D -D supplied from an external source by a decoder Therefore, the reference voltage VLCD can be set in a plurality of stages simply by changing control data D -D to a user specified value. As the twelve resistor elements connected in series are formed on the same semiconductor substrate, display contrast can be adjusted without requiring any external components attached to a liquid crystal driving integrated circuit

A master (1) and a slave (3) are connected via a transmission line (5) for sending a clock CL; another transmission line (6) for bidirectionally sending data DT; and still another transmission line (7) for sending a control signal CE. Having turned a control signal CE into 'L,' the master (1) transmits an address code as data DT to the slave (3). Referring to the content of the transmitted address code, the slave (3) detects whether it is a data transmission from the master (1) to the slave (3) or vice versa. While a control signal CE remains 'H,' data transmission takes place. Data output from the slave (3) to the data line (6) is managed by a bus driver (22). The bus driver (22) is turned off during a period from when the clock CL became 'H' to when a control signal CE becomes 'L' after data transmission so that data transmission from the master (1) will not be adversely affected.

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Tochigi-ken, Japan

Shuji Motegi