Nippon Telegraph and Telephone Corporation

Nec Corporation

Shuji Kubota

Shuzo Kato

Takatoshi Sugiyama

Masahiro Morikura

Toshiharu Yagi

Katsuhiko Kawazoe

Shunji Honda

Kiyoshi Enomoto

In a semiconductor integrated circuit provided with a circuit for testing an input buffer threshold voltage, an output node of a first logic gate having its output logic value determined by an output signal of an input buffer, and an output node of a second logic gate having its output logic value determined by a condition setting signal from an external source, are connected to a common signal line. When a standardized voltage for discriminating the threshold voltage is applied to the input buffer, if the input buffer malfunctions, the output signal of the first logic gate collides with the output signal of the second logic gate on the common signal line, so that a power supply current greatly increases.

Semiconductor integrated circuit with a test circuit for input buffer

A serial-parallel converter is arranged to convert an information sequence into a plurality of bit sequences. Two convolutional encoders are provided which respectively receive bit sequences from the serial-parallel converter. Each of the two convolutional encoders outputs first and second bit sequences. First parallel-serial converter receives the first bit sequences and converts them into third bit sequence, while second parallel-serial converter receives the second bit sequences and converts them into fourth bit sequence. The third and fourth bit sequences are used to modulate two carriers with a phase difference of .pi./2 radians.

Error control coding arrangement for digital communications system

In a simple decoder which decodes convolutional codes of constraint length K and coding rate n/m, encoded data which is supplied thereto in steps of m bits are distributed, bit by bit, to m shift registers each having x=[(K-1)/(m-n)] series-connected shift stages. Here, [p] means the minimum integer equal to or larger than a real number p. The connection of n modulo-2 addition circuits to all the shift stages of all the shift registers is defined by n decoding generative vectors which define n decoding generative polynomials. The modulo-2 addition circuits perform modulo-2 additions of the outputs of the shift stages connected thereto and output n results of additions as decoded results of n bits. The n decoding generative vectors are selected from decoding generative vectors of N rows which are obtained as an inverse matrix of a square matrix whose elements are N.times.N coefficients which define N=mx convolutional code generating polynomials.

Method and circuit for decoding convolutional codes

A digital communication system using superposed transmission of high and low speed digital signals capable of transmitting superposed high and low speed digital signals through an identical frequency band efficiently by increasing a simultaneously transmittable number of channels in the low speed digital signals, while achieving the practically reasonable bit error rate performances for both the high speed digital signals and the low speed digital signals. In this system, the low speed digital signals are transmitted in a form of spread spectrum signals and the high speed digital signals are cancelled out from the superposed transmission signals in obtaining the output low speed digital signals by using the phase inverted replica of the high speed digital signals to be combined with the superposed transmission signals, so that it becomes possible to increase a number of channels for the low speed digital signals, while achieving the practically reasonable bit error rate performances for both the high speed digital signals and the low speed digital signals.

Digital communication system using superposed transmission of high speed

This invention relates to a convolutional encoder which encodes original data into convolutional codes by using a multinomial from which predetermined terms of the generation multinomial for generating the original convolutional codes are eliminated to thereby achieve high transmission efficiency as well as high error correcting capacity. The maximum likelihood decoder which is provided on the receiver side to correspond to the encoder can decode in maximum likelihood by calculating the branch metrics of received encoded data and decode the original data in correspondence to the coding rate of the original data with those branch metrics.

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Kanagawa, Japan

Shuji Kubota