Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Other

Hitachi Ulsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Quantum Biosystems Inc.

Ihi Corporation

Hitachi Engineering Co., Ltd.

Trecenti Technologies, Inc.

Elpida Memory, Inc.

Hitachi Vlsi Engineering Corp.

Shuji Ikeda

Hideo Miura

Toshiaki Yamanaka

Naotaka Hashimoto

Yasuko Yoshida

Koichiro Ishibashi

Satoshi Meguro

Norio Suzuki

Yutaka Hoshino

Atsuyoshi Koike

Akihiro Shimizu

Norio Ishitsuka

Kazushige Sato

Shinichiro Mitani

Kenichi Kikushima

Akira Fukami

Masaya Iida

Kenichi Osada

Tomio Iwasaki

Soichiro Hashiba

Kenichi Kuroda

Masayuki Kojima

Shinji Nishihara

Katsuro Sasaki

Shinichi Horibe

Takashi Hashimoto

Masataka Minami

Masayuki Suzuki

Hiromi Abe

Nobuyuki Moriwaki

Kouichi Nagasawa

Kazushi Fukuda

Shiro Kamohara

Akira Takamatsu

Yutaka Kobayashi

Hiroyuki Ohta

Atsushi Hiraishi

Isao Yoshida

Masatoshi Morikawa

Hiroshi Moriya

Seigou Yukutake

Shigeru Takahashi

Tomoyuki Miyake

Asao Nishimura

Shoji Shukuri

Yasuhiro Taniguchi

Shinichi Fukada

Hiroshi Momiji

Kozo Watanabe

Keiichi Yoshizumi

Hirohiko Yamamoto

Hisayuki Kato

Akio Nishida

Hiroyuki Uchiyama

Kunio Uchiyama

Yoshio Sakai

Yasuhisa Shimazaki

Masashi Sahara

Norio Nakagawa

Atsushi Ogishima

Yukihiro Kumagai

Keiji Okamoto

Kotaro Nishimura

Shinichi Ishida

Kyoichiro Asayama

Nobuyoshi Tanimura

Mark F Oldham

Norio Hasegawa

Eric S Nordman

Satoshi Sakai

Kousuke Okuyama

Atsushi Hiraiwa

Toshifumi Takeda

Kota Funayama

Sadayuki Morita

Osamu Inoue

Hiromi Shimazu

Takayuki Kanda

Kazuyuki Suko

Makoto Saeki

Kenji Kanamitsu

Michimasa Funabashi

Kazuo Yoshizaki

Hideki Tanaka

Hideyuki Matsuoka

Shinichiro Kimura

Toshiaki Masuhara

Osamu Minato

Eiichi Murakami

Fumio Ootsuka

Eiji Takeda

Takahiro Onai

Terunori Warabisako

Masaaki Aoki

Takashi Nishida

Katsuhiko Ichinose

Shoji Hanamura

Hiroki Yoshizawa

Masahito Takahashi

Takashi Aoyagi

A method of manufacturing a Ni alloy part includes a solution treatment step of solution treating a sintered compact, which is obtained by sintering and molding a precipitation hardening Ni alloy powder by metal injection molding, by allowing the sintered compact to hold at a temperature of not lower than 1050&#xb0; C. but not higher than 1250&#xb0; C. for one hour to five hours, followed by rapidly cooling to room temperature, where the precipitation hardening Ni alloy powder, and an aging treatment step of aging-treating the solution-treated sintered compact by allowing the solution-treated sintered compact to hold at the temperature of not lower than 600&#xb0; C. but not higher than 800&#xb0; C., followed by cooling to room temperature.

Method of manufacturing Ni alloy part

Method of manufacturing ni alloy part

A system for detecting a biomolecule comprises a nano-gap electrode device including a first electrode and a second electrode adjacent to the first electrode. The first electrode can be separated from the second electrode by a nano-gap that is dimensioned to permit the biomolecule to flow through the nano-gap. The nano-gap can have at least a first gap region and a second gap region. The second gap region can be oriented at an angle that is greater than zero degrees with respect to a plane having the first gap region. The system can further include an electrical circuit coupled to the nano-gap electrode device. The electrical circuit can receive electrical signals from the first electrode and the second electrode upon the flow of the biomolecule through the nano-gap.

Nano-gap electrode pair and method of manufacturing same

Methods for forming electrodes for use in nano-gap electrodes are provided. Such methods can be used to form electrodes for use in devices that can be used to sense or detect biomolecules, such as in biomolecule sequence applications.

Methods for forming nano-gap electrodes for use in nanosensors

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NWand are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

Semiconductor integrated circuit device

A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NWand are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NWand are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.

Semiconductor integrated circuit device including SRAM cell array and a wiring layer for supplying voltage to well regions of SRAM cells provided on a region exterior of SRAM cell array

In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs(P) for leading out electrodes on a source region, a drain regionand leach-through layers(), to which a first layer wirings(M) are connected and, further, backing second layer wiringstoare connected on the conductor plugs(P) to the first layer wirings(M).

Semiconductor device including a power MISFET

Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NWand are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

Semiconductor integrated circuit device including SRAM memory cells having two P-channel MOS transistors and four N-channel MOS transistors and with four wiring layers serving as their gate electrodes

Semiconductor device including a power MISFET and method of manufacturing the same

A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Semiconductor integrated circuit device and process for manufacturing the same

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Method of fabricating semiconductor integrated circuit device

Growing community of inventors

Koganei, Japan

Shuji Ikeda