Matsushita Electric Industrial Co., Ltd.

Shuji Hirao

Kousaku Yano

Hisashi Ogawa

Isao Miyanaga

Masanori Fukumoto

Yuka Terai

Mitsuru Sekiguchi

Noboru Nomura

Hideko Okada

Tetsuya Ueda

Takeshi Harada

Tomoyasu Murakami

Tatsuo Sugiyama

Michinari Yamanaka

Takenobu Kishida

Atsushi Ikeda

Kazushi Nii

Kazunori Tsuji

After bubbles adsorbed to a substrate are removed by rotating the substrate in a plating solution at a higher speed or after the wettability of the surface of the substrate to be plated is improved before the substrate is immersed in the plating solution, the substrate is rotated in the plating solution at a lower speed so that a plating process is performed with respect to the substrate.

Method and apparatus for plating substrate

After a thin first conductive film is formed on a barrier film having a crystal structure, a second conductive film is formed on the first conductive film. Thereafter, the first conductive film and the second conductive film are heated such that the first and second conductive films are integrated to form a third conductive film.

Production method of semiconductor device

A first electrode and a first insulating layer of electrode insulation are formed on a first semiconductor substrate. A second electrode and a second insulating layer of electrode insulation are formed on a second semiconductor substrate. The first semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement. Likewise, the second semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement, wherein the pattern of the second semiconductor substrate has a phase shift of 180 degrees with respect to the pattern of the first semiconductor substrate. The first and second semiconductor substrates are bonded together with their patterns in engagement.

Semiconductor device and associated fabrication method

On an insulating substrate are formed first aluminum interconnections. In openings formed in a silicon dioxide film are formed unit cells each consisting of a tungsten electrode and an aluminum alloy electrode containing silicon. Over the silicon dioxide film are formed a large number of linear second aluminum interconnections which are orthogonal to the first aluminum interconnections. At the individual intersections of the first and second aluminum interconnections are disposed the unit cells so as to compose a memory cell array. When a large current is allowed to flow through the unit cell, silicon in the aluminum alloy electrode moves in a direction opposite to the current flow and is precipitated in the aluminum electrode in the vicinity of the interface with the tungsten electrode, resulting in an increase in resistance value. When a large current is allowed to flow through the unit cell in the opposite direction, silicon is diffused, resulting in a reduction in resistance value. Data can be read by measuring the magnitude of the resistance value with an extremely small current and judging whether it is in a high state or in a low state.

Method for forming a memory device by utilizing variations in resistance

A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.

Method of fabricating a semiconductor device

Memory device with tungsten and aluminum interconnects

Method of fabricating capacitor or contact for semiconductor device by

After accumulating a BPSG film layer on a silicon substrate, a first Al--Si--Cu film layer, a W film layer and a second Al--Si--Cu film layer are successively accumulated on this BPSG film layer. A resist pattern with wide-width and narrow-width pattern portions is formed on the second Al--Si--Cu film layer. The wide-width pattern portion is provided at a position corresponding to a contact for connecting a first-layer metallic wiring and a second-layer metallic wiring, while the narrow-width pattern portion is provided at a position corresponding to a wiring portion for the first-layer metallic wiring. After applying first etching on the second Al--Si--Cu film layer with a mask of the resist patter, second etching is applied on the W film layer. Thereafter, by applying third etching, the resist pattern remaining on the first-layer metallic wiring is removed and the first Al--Si--Cu film layer is transfigured into a tall metallic film portion and a short metallic film portion. After accumulating an inter-layer insulating film layer on the first Al--Si--Cu film layer, etchback is applied on this inter-layer insulating film layer until the top of the tall metallic film portion is bared. Then, the second-layer metallic wiring is formed on the inter-layer insulating film layer so that the second-layer metallic wiring is connected with the tall metallic film portion.

Method for forming a multi-layer metallic wiring structure

Growing community of inventors

Osaka, Japan

Shuji Hirao