Fujitsu Semiconductor Limited

Socionext Inc.

Shuji Hamada

Atsuo Takatori

Yukinori Setohara

Mitsuhiro Hirano

A circuit design support method includes obtaining shared circuit information indicating various types of shared circuits each executing at least any one of various types of logical computations and causing plural signal lines to share an observation point at which a signal value is observable; determining for each of the signal lines to be observed in a circuit under-design, a value based on controllability representing ease of control to set a value of the signal line to be a specific value; selecting based on the obtained shared circuit information, any one shared circuit among the various types of shared circuits; and generating correlation information that correlates each input terminal of the selected shared circuit with a signal line among the signal lines to be observed and whose value determined therefor is equal to a non-controlling value of a logical computation executed for an input signal input into the input terminal.

Circuit design support method, computer product, and circuit design support apparatus

An electric circuit includes a delayed clock generation circuit to which a first clock is supplied and which is configured to generate a first delayed clock and a second delayed clock, the first delayed clock being the first clock delayed by a first delay amount, and the second delayed clock being the first clock delayed by a second delay amount different from the first delay amount, an OR gate configured to receive the first clock, the first delayed clock, and the second delayed clock as inputs and to output a second clock, and a scan circuit to which the second clock is supplied.

Electric circuit and semiconductor device

Logic circuitry has a test point to detect a signal about a delay fault propagating on a logic path between an input terminal and an output terminal, the test point being coupled to the logic path, wherein the test point includes a delay component to delay timing to detect the signal about a delay fault propagating on the logic path by predetermined time.

Logic circuitry and recording medium

A logic circuit includes a gated clock buffer including a control node, being set in either a first state or a second state in response to an input signal applied to the control node, outputting an input clock signal supplied as an output signal in the first state, and fixing an output signal to a constant value in the second state, a plurality of scan flip-flops receiving the output signal of the gated clock buffer, and included in at least part of a scan chain, and a combinational logic circuit coupled to at least one of the plurality of scan flip-flops.

Growing community of inventors

Kawasaki, Japan

Shuji Hamada