Nec Corporation

Alps Alpine Co., Ltd.

Alps Alpineco., Ltd.

Alps Electric Co., Ltd.

Shuji Fujiwara

Makoto Hayashi

Toshiyuki Hirota

Hirohito Watanabe

Masanobu Zenke

Fumiki Aiso

Tatsuaki Kawase

Nobuyuki Ninomiya

Kenji Okamura

Tomoya Endo

Hidekazu Kato

Kiyotaka Sakamoto

Tomoyasu Nagano

Takao Katuyama

An operation device includes a housing, a tiltable cylindrical operation member having a step portion on an inner circumferential surface, a first holding member which is held by the housing and rotatable in a first direction in accordance with a tilting operation of the operation member, a first detecting portion for detecting a rotation of the first holding member, and a returning mechanism disposed inside the operation member to return the tilted operation member to an initial position, wherein the returning mechanism includes an actuator, a slide member having a first cam surface at one end, a cam member having a second cam surface at one end which faces the first cam surface, a first elastic member, and a second elastic member.

Operation device

A power generation device includes a push member configured to move back and forth in a first pushing direction and a second pushing direction to push a rotating body to move between a first stable attitude and a second stable attitude, an operation member configured to move in a first direction and a second direction, and a switching spring member arranged between the operation member and the push member. The switching spring member is configured to urge the push member in the first pushing direction to cause the rotating body to move toward the second stable attitude when the operation member moves in the first direction, and the switching spring member is configured to urge the push member in the second pushing direction to cause the rotating body to move toward the first stable attitude when the operation member moves in the second direction.

Power generation device

There is provided a method of manufacturing a semiconductor device having a MOS transistor formed on a silicon substrate, and a stacked capacitor constituted by an information storage electrode provided above the MOS transistor through an insulating interlayer and a counter-electrode separated from the information storage electrode due to the presence of a capacitor insulating film. In this method, the capacitor is formed by adding an impurity in a silicon oxide film which is formed on the insulating interlayer and used to shape the information storage electrode, and performing etching by using a chemical solution containing phosphoric acid, sulfuric acid, nitric acid, or a solution mixture thereof, or a chemical solution containing a solution mixture of an aqueous ammonia solution and a hydrogen peroxide solution to selectively remove the silicon oxide film added with the impurity.

Method of measuring semiconductor device

A first amorphous silicon layer is formed to connect to a portion of a capacitor contact plug, and then a second amorphous silicon layer and a third amorphous silicon layer are formed thereon. The first and the third amorphous silicon layers are formed so that they have a lower impurity concentration than that in the second amorphous silicon layer. HSG (hemispherical grain) is grown on surfaces of the first and the third amorphous silicon layers, and subsequently an impurity is diffused from the second amorphous silicon layer to the HSG. In such a method for producing a capacitor, the size of the HSG can be appropriately and uniformly controlled, and depletion in the HSG is prevented.

Method for producing capacitor having hemispherical grain

In a process of forming hemi-spherical silicon grains on an amorphous silicon film in accordance with the 'crystal nucleation' process, in order to form crystal nuclei on a top surface and a side surface of the amorphous silicon film, SiH.sub.4 is irradiated onto the top and side surfaces of the amorphous silicon film at a stabilized temperature which is lower than, by at least 5.degree. C., an annealing temperature for growing the hemi-spherical silicon grains from the crystal nuclei, with the result that it is possible to suppress or retard the growth of the crystals growing into the amorphous silicon film from a boundary between the amorphous silicon film and an interlayer insulator film. Thereafter, the amorphous silicon film having the crystal nuclei thus formed on the surface thereof is annealed at the annealing temperature so that the hemi-spherical silicon grains are formed on the whole surface of the top and side surfaces of the amorphous silicon film.

Process for forming a capacitor incorporated in a semiconductor device

A method of manufacturing a semiconductor device contains a first treatment step of removing a silicon oxide film on a semiconductor substrate (15) in a rare hydrofluoric acid treatment device (12), a second treatment step of forming hemispherical grained silicon on the semiconductor substrate (15) in an HSG-Si forming device (13), and a step of moving the semiconductor substrate (15) treated in the first treatment step to the HSG-Si forming device (13) by means of a semiconductor substrate moving device (14), wherein filtering an air in the semiconductor substrate moving device (14) is conducted so that an amount of organic materials which adhere onto a surface of the semiconductor substrate (15) during a process to the second treatment step is set to 1 ng/cm.sup.2 or less.

Method for manufacturing semiconductor device and semiconductor device

A method of manufacturing a cylindrical stacked electrode, which comprises the steps of forming a silicon film on a semiconductor substrate, forming an insulating film over said silicon film, etching said insulating film to open a first hole that reaches the semiconductor substrate lying beneath said silicon film, forming a second hole with a wider diameter than said first hole through said insulating film and, concurrently with that, opening a contact hole using said silicon film as a mask, burying said contact hole and, in addition, forming an amorphous silicon film into a shape of a cylindrical stacked electrode, forming a second insulating film on said amorphous silicon film to bury said second hole, etching said second insulating film to the level of the amorphous silicon surface, etching said amorphous silicon film to the level of the first insulating film surface, removing said insulating film, and removing a portion of the silicon film formed on the semiconductor substrate that is all but an area directly below said cylindrical stacked electrode.

Manufacturing method of cylindrical stacked electrode

In a capacitor incorporated in a semiconductor device, a capacitor lower plate is formed of a first amorphous silicon film on an interlayer insulator film and a second amorphous silicon film stacked on the first amorphous silicon film. A crystallization preventing film is formed between the first and second amorphous silicon films, or alternatively, the first amorphous silicon film is formed to have an impurity concentration lower than that of the second amorphous silicon film. A stacked structure formed of the first and second amorphous silicon films is patterned into a capacitor lower plate having a top surface and a side surface, and hemispherical grains are formed on not only the top surface but also the side surface of the patterned stacked structure. In this process, crystalline growth from the interlayer insulator film is prevented by the crystallization preventing film or by the fact that the first amorphous silicon film is formed to have an impurity concentration lower than that of the second amorphous silicon film. Thus, concaves and convexes in the form of hemispherical grains are uniformly formed on not only the top surface but also the side surface of the patterned stacked structure, so that a remarkably increased capacitance can be obtained.

Capacitor incorporated in semiconductor device having a lower electrode

A phosphorous doped amorphous silicon storage node electrode is treated with heat so as to be converted into a phosphorous doped polysilicon storage electrode, and the heat causes the phosphorous to be diffused into a shallow n-type source region of an n-channel enhancement type switching transistor; to protect the shallow n-type source region from the phosphorous, a phosphorous/oxygen doped amorphous silicon layer is formed between the shallow n-type source region and the phosphorous-doped amorphous silicon storage node electrode, and the oxygen decelerates the phosphorous diffused therethrough, thereby decreasing the amount of phosphorous diffused into the n-type shallow source region.

Semiconductor device having oxygen-doped silicon layer so as to restrict

In a wafer rinsing and drying method, a wet-treated wafer is put in a treating bath located in a closed chamber and is rinsed by a rising stream of a deionized water while supplying from position higher than the treating bath a vapor of IPA which is a water soluble solvent acting to lower the surface tension of the deionized water, so that the surface tension of the deionized water bath is weakened, and the extremely fine particles remaining on the surface of the deionized water bath is removed together with the deionized water overflowing from an upper edge of the treating bath. Thereafter, the supplying of the deionized water is stopped, but the IPA vapor is blown on to the surface of the deionized water from the high position for a predetermined period of time, so that a stationary deionized water bath is formed and a uniform and thick liquid IPA layer is formed on the surface of the stationary deionized water bath. In this condition, the wafer is pulled up so that the deionized water on the wafer surface is replaced with the liquid IPA. Thereafter, the deionized water is exhausted from the treating bath, and the closed chamber is evacuated so that the wafer is dried.

Method for rinsing and drying a substrate

In a method for forming a cylindrical capacitor lower plate in a semiconductor device, a first insulating film, a first conducting film and a second insulating film are formed on a principal surface of a semiconductor substrate in the named order. A patterned photoresist film is formed on the second insulating film, and the second insulating film is patterned by an anisotropic etching using the photoresist film as a mask. After the photoresist film is removed, the first conducting film is patterned by an etching using the patterned second insulating film as a mask. Thereafter, a second conducting film is deposited on a whole surface, and then, the second conducting film is anisotropically etched so that a remaining second conducting film is left on a side surface of the patterned first conducting film. The patterned second insulating film is removed, so that the remaining second conducting film is left in the form of a sidewall which is upright from a periphery of the patterned first conducting film.

Growing community of inventors

Tokyo, Japan

Shuji Fujiwara