Denso Corporation

Shuji Agatsuma

Kiyoshi Nagata

Masaya Ootake

Nobumasa Ueda

Sadahiro Akama

Masahiro Kuroda

Takuya Harada

Akimasa Niwa

Yoshinori Teshima

Takayuki Aono

Kyoichi Suzuki

A motor driving apparatus has a loss-of-synchronism monitoring circuit that monitors the rotation of a rotary machine such as a brushless DC motor to detect a sign of transition to a state of loss of synchronism. When the sign is detected, an energization control circuit temporarily stops driving of the rotary machine to bring it into a free running state, and thereafter carries out control so as to resume driving of the rotary machine. Further, the motor driving apparatus has an inverter and a drive control circuit that controls switching operation of the inverter based on rotation of the rotary machine.

Apparatus and method for driving rotary machine

A multiprocessor system has a plurality of CPUs with respective local buses, and a memory which stores a plurality of programs to be executed by the CPUs and is connected to a common bus which can be accessed via the local buses, each local bus being connected to a CPU identification register which stores an identification value for identifying the corresponding CPU. When a program which is specific to a CPU is to be executed by that CPU, the corresponding identification value is read out from the identification register of the CPU and is judged, and branching to the appropriate program is performed based on the judgement result.

Multiprocessor system having a plurality of control programs stored in a continuous range of addresses of a common memory and having identification registers each corresponding to a processor and containing data used in deriving a starting address of a CPU-linked interrupt handler program to be executed by the corresponding processor

A memory control apparatus for controlling the operation of a memory array in a serial memory employs a command control section for registering the bits of an instruction which is received as an externally supplied set of serial data in conjunction with a corresponding series of cycles of a clock signal, with each set of serial data formatted as a command data portion preceded by a start bit, whereby the shifting of the start bit into the MSB stage of the shift register is detected and used to terminate supplying the clock signal to the shift register, thereby eliminating the use of a counter circuit. Any additional clock signal cycle following shifting of the start bit into the MSB stage of the shift register is detected, so that operating errors caused by noise in the received clock signal can be reliably eliminated.

Memory control apparatus for serial memory

Growing community of inventors

Toyohashi, Japan

Shuji Agatsuma