Seagate Technology Incorporated

Shuiyuan Huang

Song Sheng Xue

Michael Xuefei Tang

Dimitar Velikov Dimitrov

Haiwen Xi

Antoine Khoueir

Insik Jin

Ming Sun

Dexin Wang

Xuguang Alan Wang

Yang Li

Harry Hongyue Liu

Olle Gunnar Heinonen

Brian Lee

John D Stricklin

Maroun Khoury

Yongchul Ahn

Ivan Petrov Ivanov

Peter Nicholas Manos

Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate.

Non-volatile multi-bit memory with programmable capacitance

A magnetic memory element that has a stress-induced magnetic anisotropy. The memory element has a ferromagnetic free layer having a switchable magnetization orientation switchable, a ferromagnetic reference layer having a pinned magnetization orientation, and a non-magnetic spacer layer therebetween. The free layer may be circular, essentially circular or nearly circular.

Memory cell with stress-induced anisotropy

A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.

Magnet-assisted transistor devices

Methods for making a programmable metallization memory cell are disclosed.

Programmable metallization memory cells via selective channel forming

A programmable metallization memory cell that has an apertured insulating layer comprising at least one aperture therethrough positioned between the active electrode and the inert electrode. Superionic clusters are present within the at least one aperture, and may extend past the at least one aperture. Also, methods for making a programmable metallization memory cell are disclosed.

Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed.

Non-volatile memory with programmable capacitance

Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level.

Active protection device for resistive random access memory (RRAM) formation

Programmable metallization memory cells that have an inert electrode and an active electrode positioned in a non-overlapping manner in relation to a substrate. A fast ion conductor material is in electrical contact with and extends from the inert electrode to the active electrode, the fast ion conductor including superionic clusters extending from the inert electrode to the active electrode. A metal layer extends from the inert electrode to the active electrode, yet is electrically insulated from each of the inert electrode and the active electrode by the fast ion conductor material. Methods for forming programmable metallization cells are also disclosed.

Planar programmable metallization memory cells

Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at least two states and is proximate the source region. A second solid electrolyte cell is over the insulating layer and has a capacitance or resistance that is controllable between at least two states and is proximate the drain region. An insulating element isolates the first solid electrolyte cell from the second solid electrolyte cell. A first anode is electrically coupled to the first solid electrolyte cell. The first solid electrolyte cell is between the anode and the insulating layer. A second anode is electrically coupled to the second solid electrolyte cell. The second solid electrolyte cell is between the anode and the insulating layer. A gate contact layer is over the substrate and between the source region and drain region and in electrical connection with the first anode and the second anode. The gate contact layer is electrically coupled to a voltage source.

Growing community of inventors

Apple Valley, MN, United States of America

Shuiyuan Huang