Sharp Kabushiki Kaisha Corporation

Shuichiro Kouchi

Yasuaki Hirano

Yasuhiro Hotta

Yasumichi Mori

Yoshihisa Sekiguchi

A non-volatile semiconductor memory device includes a memory cell array including a plurality of memory cells, wherein information is writable to each of the plurality of memory cells and information is erasable from each of the plurality of memory cells, and the plurality of memory cells are grouped into at least one memory block; and a write and erasing section for performing a program write operation to a prescribed memory cell in one memory block in a prescribed voltage condition and for performing an erasing operation with respect to the memory cells in the one memory block, wherein the write and erasing section performs a pre-erasing write operation to the memory cells in the one memory block in a voltage condition, which is different from the prescribed voltage condition, before the erasing operation is performed with respect to the memory cells in the one memory block.

Non-volatile semiconductor memory device and erasing control method thereof

In the nonvolatile semiconductor memory device of this invention, a program control circuitsets the threshold value of a first reference cell RFCby means of a write circuit WC on the basis of a result of comparing the threshold value of the first reference cell RFCwith the threshold value of a second reference cell SRC executed by a sense amplifierfor trimming. The compare of threshold values by the sense amplifierfor trimming can be executed within a shorter time than in the threshold value read operation of the first reference cell RFCTherefore, when the number of the first reference cells is increased, the threshold value adjustment time can be remarkably reduced in comparison with the prior art in which the threshold value of the first reference cell is adjusted by reading the first reference cell.

Nonvolatile semiconductor memory device

A non-volatile semiconductor memory device, is provided, which comprises a plurality of memory cells capable of electrically writing and erasing data and a voltage control section for controlling a control voltage to be applied to each of the plurality of row lines. The voltage control section comprises a storing section and a voltage output section. The storing section stores the value of the control voltage, which is calculated to permit a threshold voltage distribution to be within a predetermined range, in accordance with the threshold voltage distribution of the plurality of memory cells in each chip. The voltage output section outputs the control voltage having the value stored in the storing section to each of the plurality of row lines.

Non-volatile semiconductor memory device and data write control method for the same

A well voltage setting circuit has a P-MOS transistor for applying erase pulse, a first N-MOS transistor for applying a reference voltage Vss to a P-well in a shutdown sequence after erase pulse application, and a second N-MOS transistor for forcing the P-well to the reference voltage Vss during write and read. The first N-MOS transistor has a driving capacity set to about {fraction (1/50)} of that of the second N-MOS transistor, so that a time for forcing the P-well to the reference voltage Vss is long enough to prevent occurrence of local latch-up during erase.

Nonvolatile semiconductor memory well voltage setting circuit without latchup and semiconductor memory device provided with the circuit

A virtual-grounding memory cell array region and a virtual-grounding dummy cell array region are electrically isolated from each other while any increase in chip size is suppressed. An erase voltage Vers (&minus;8 V) is applied to a dummy main bit line DMBL,in a dummy cell array region,via an erase voltage supply transistor,. A negative voltage (&minus;8 V) is applied to drains of dummy cells DCELL,, DCELL,, . . . as well as sources of dummy cells DCELL,, DCELL,, . . . within a BLOCKn through dummy sub-bit lines DSBL. By electrons being injected into the floating gates of all the dummy cells DCELL in the columns of the dummy cells DCELL,and DCELL,within the BLOCKn, the threshold of those dummy cells DCELL becomes high. Occurrence of any charging currents and leak currents from the virtual-grounding memory cell array region to the floating capacitance of the dummy cells is prevented.

Nonvolatile semiconductor storage device capable of electrically isolating dummy cell array region from memory cell array region

A semiconductor memory device includes a main memory section, a redundant memory section, a memory cell selection section, a sensing amplification section, a data replacement section, and a data selection section. The redundant memory section includes a replacement cell data memory section for storing replacement cell data to replace cell data in a prescribed memory cell in the main memory section, and a control signal generation section for generating a control signal based on an input address. The memory cell selection section simultaneously selects prescribed cells as a plurality of memory cells corresponding to a prescribed page in the main memory section based on the input address. The sensing amplification section simultaneously senses cell data corresponding to a selected plurality of memory cells as page data. A supply of the replacement cell data and the control signal from the redundant memory section to the data replacement section is performed in a time period from the time when the input address is determined until a time when the page data to be output from the sensing amplification section is determined.

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Tenri, Japan

Shuichiro Kouchi