Buffalo Inc.

Buffalo Memory Co., Ltd.

Meisei Gakuen

Shuichiro Azuma

Kazuki Makuni

Takayuki Okinaga

Noriaki Sugahara

Yu Nakase

Yosuke Takata

Yoichi Sato

Takeshi Kotegawa

Kanji Otsuka

A storage apparatus includes: a memory that stores data and main management information, the main management information identifying a physical address of the data; and processing circuitry configured to generate preliminary management information that includes information of the same content as the main management information, and select, as use management information, any one of the main management information and the preliminary management information upon start of the storage apparatus. Access to the data stored in the memory is performed using the selected use management information.

Storage apparatus and method that generates preliminary management information including the same content as main management information for identifying physical address of data

A storage device comprises a flash memory and processing circuitry. The processing circuitry is configured to divide a storage area into pages to manage the storage area, and deletes each of the blocks including a plurality of pages. The processing circuitry receives a write instruction including address information specifying a writing location of the data, and stores, with respect to a plurality of groups in which each group includes one or more blocks, a plurality of group identification information each identifying a group and information specifying blocks included in the group in association with each other. The processing circuitry performs a predetermined calculation to obtain group identification information, and identifies a group including a block including pages onto which data is to be written according to the write instruction. Finally, the processing circuitry writes the data onto the pages of the block included in the group identified.

Storage device, control method of storage device, and storage medium

A storage device including a flash memory, and circuitry that manages a logical address and a physical address so as to be converted using a conversion table, writes a logical address and old and new information indicating a timing when the data is written, into the physical address together with the data, writes at least latest old and new information of the old and new information written in the block into a predetermined page of the block, and reestablishes the conversion table by arranging the logical address recorded in each page included in the block and the physical address corresponding to the logical address in association with each other, in chronological order of the latest old and new information read out from each block of the flash memory, at a predetermined reestablishment timing for performing reestablishment of the conversion table.

Storage device and data management method of storage device

A storage device includes a first memory which stores data including activation data necessary to activate a host device, a second memory, and a controller which performs writing and reading operation of data stored in the first memory based on a request from the host device; acquires address information including an address and data amount of data in the first memory, for which a read request is previously issued from the host device at activation of the host device; at activation of the storage device, reads data including at least the activation data from the first memory based on the address information and store the data in the second memory; and in response to a read request issued from the host device, transmits the data stored in the second memory to the host device.

Storage device, information processing system, method of activating storage device and program

A semiconductor device comprising a plurality of semiconductor chips and a plurality of electric wirings. The plurality of semiconductor chips are stacked in a first direction, each semiconductor chip of the plurality of semiconductor chips including a plurality of conductive pads that are aligned in an aligning direction, orthogonal to the first direction. The plurality of semiconductor chips are stacked such that each semiconductor chip is shifted from an adjacent semiconductor chip of the plurality of semiconductor chips by a first predetermined interval in the aligning direction and shifted from the adjacent semiconductor chip by a second predetermined interval in a second direction orthogonal to both the first direction and the aligning direction. The plurality of electric wirings electrically connect the plurality of conductive pads of every other semiconductor chip of the plurality of semiconductor chips, respectively.

Semiconductor device including plural semiconductor chips

An arithmetic logic operation device including a memory device configured to store a lookup table and receive an input of a bit string N bits long, N being an integer of at least 2, the input bit string representing an address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device is accessed to output the bits included in the data stored at the address represented by the received bit string. The arithmetic logic device achieves arithmetic processing in a relatively short time on a relatively small circuit scale.

Device for logic operation

A solid state drive (SSD) device using a flash memory and including a non-volatile memory that differs in type from the flash memory. The SSD device receives data to be written to the flash memory; stores the received data in the non-volatile memory; stores the data stored in the non-volatile memory to the flash memory; and stores, in the non-volatile memory, flow data indicating a flow of tasks to be undertaken while storing the received data in the non-volatile memory and storing the data stored in the non-volatile memory to the flash memory.

Solid-state drive device

An information processing apparatus including a NAND type flash memory; circuitry configured to control writing/reading of data to/from the NAND type flash memory; and an interface configured to connect the information processing apparatus to a host apparatus. The circuitry is configured to determine whether to erase data stored in a specific area within the NAND type flash memory by overwriting the data based on whether an overwrite command is received from the host apparatus via the interface; and erase a physical block including the specific area when it is determined to erase the data by removing electric charges in the NAND type flash memory in the physical block including the specific area.

Growing community of inventors

Nagoya, Japan

Shuichiro Azuma