Hitachi, Ltd.

Disco Corporation

Hitachi Microcomputer Engineering, Ltd.

Shuichi Torii

Ryohei Yamamoto

Yutaka Kobayashi

Kazuya Hirata

Yoshimune Hagiwara

Kentaro Iizuka

Katsuaki Takagi

Yuzo Kita

Koyo Honoki

Kazuyoshi Ogawa

Tamotu Arai

A method for manufacturing an SiC wafer from an SiC ingot includes a verifying step of applying a test laser beam to the SiC ingot in a predetermined area with the focal point of the test laser beam set inside the SiC ingot at a predetermined depth from the end surface of the SiC ingot. The test laser beam has a transmission wavelength to SiC, thereby forming a test separation layer inside the SiC ingot at the predetermined depth. The test separation layer has a test modified portion where SiC is decomposed into Si and C and test cracks extend from the test modified portion along a c-plane in the SiC ingot. Whether or not the test cracks have been properly formed is verified. When verifying, the power of the test laser beam is changed to set a proper power at which the test cracks are properly formed.

SiC wafer manufacturing method and SiC wafer manufacturing apparatus

Disclosed herein is a laser processing apparatus for forming a separation layer inside an ingot by applying a laser beam to an end surface of the ingot in the condition where the focal point of the laser beam is set inside the ingot, the laser beam having a transmission wavelength to the ingot. The laser processing apparatus includes a holding unit for holding the ingot, a moving unit for moving the holding unit in a direction parallel to the end surface of the ingot held by the holding unit, a laser beam applying unit for applying the laser beam to the ingot held by the holding unit, an imaging unit for detecting the position of the ingot in the direction parallel to the end surface of the ingot, and a height detecting unit for detecting the height of the end surface of the ingot held by the holding unit.

Laser processing apparatus

An integrator circuit comprising reset means by which, when it is detected that an integrator output V.sub.p for an input analog signal coincides with a plus or minus reference value, the integral output is reset to the vicinity of the middle of the plus and minus reference values, in effect, without interrupting the integrating operation; a circuit which produces a pulse each time coincidence is detected; and a circuit which produces a direction signal indicating whether the coincidence results from an increase or a decrease of the integral input. The pulses produced in the state in which the direction signal is indicating an increase are counted up, and the pulses produced in the state in which the direction signal is indicating a decrease are counted down, whereby the precise integral value of the input analog signal can be detected.

Circuit for integrating analog signal and converting it into digital

A voltage dividing circuit comprises a plurality of series-connected insulated-gate FETs, each having its gate and drain short-circuited with each other and its source and substrate short-circuited with each other. A substrate in which one FET is formed is isolated from another substrate in which another FET is formed.

Voltage dividing circuit in IC structure

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Tokyo, Japan

Shuichi Torii