Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electric Ind. Co., Ltd.

Shuichi Takayama

Nobuo Higaki

Taketo Heishi

Tetsuya Tanaka

Hajime Ogawa

Shinya Miyaji

Kensuke Odani

Akira Tanaka

Kenichi Kawaguchi

Nobuki Tominaga

Masato Suzuki

Shohei Michimoto

Toshiyuki Sakata

Ryoko Miyachi

Seiichi Urushibara

Tomoo Hamada

Kazushi Yamamoto

Junko Sayama

Fumio Sumi

Yoshiyuki Iwamura

Motohide Nishibata

Kiyohiko Sumida

Keiichi Kuroda

Masanobu Morikawa

Katsuhiro Okuno

Akira Takuma

Takanori Miyashita

Hiroki Kawai

Ryoichiro Koshimura

Shoji Nagata

Hiroki Tatsumoto

Nobuo c/o Matsushita Electric Industrial Co Ltd Higaki

A control apparatus which is inexpensive and highly effective in shortening a start-up time, a method of controlling the control apparatus, and a digital broadcast receiving apparatus are provided. The control apparatus includes: a control microcomputer; at least one device; and a ROM which stores a simple control program, a main body program, and a boot loader. The simple control program includes an interrupt program having an interrupt for starting the at least one device so that the at least one device is activated, accepts an interrupt signal requesting for the interrupt from the at least one device during loading of the main body program, and performs the interrupt.

Control apparatus, method of controlling control apparatus, and digital broadcast receiving apparatus

A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a 'if' conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.

Compiler apparatus with flexible optimization

A broadcast receiving apparatus in the present invention includes: a first audio data characteristics extracting unit extracting a first soundless period and first interval information from first audio data included in the first service; a second audio data characteristics extracting unit extracting a second soundless period and second interval information from second audio data included in the second service; a simulcast determining unit determining whether or not the broadcast waves are simulcast by comparing the first interval information with the second interval information; and a broadcasting switching control unit switching between (i) the output of the audio data and the video data included in the first service and (ii) the output of the audio data and the video data included in the second service based on a result of the determination by the simulcast determining unit.

Broadcast receiving circuit and broadcast receiving apparatus

A 32-bit instructionis composed of a 4-bit format field, a 4-bit operation field, and two 12-bit operation fieldsand. The 4-bit operation fieldcan only include (1) an operation code 'cc' that indicates a branch operation which uses a stored value of the implicitly indicated constant registeras the branch address, or (2) a constant 'const'. The content of the 4-bit operation fieldis specified by a format code provided in the format field

Processor for executing highly efficient VLIW

The digital broadcast receiving apparatus according to the present invention includes: a first decoding unit which decodes video data of a first digital broadcast and outputs first video data that is decoded; a second decoding unit which decodes video data of a second digital broadcast and outputs second video data that is decoded; and a selection unit which selects one of the first video data and the second video data, and the first decoding unit outputs the first video data synchronous with a referential clock when the first video data is selected by the selection unit, and the first decoding unit outputs the first video data with timing delayed or accelerated by as much as an offset value with respect to timing of predetermined periodicity when the first video data is not selected by the selection unit.

Digital broadcast receiving apparatus, semiconductor integrated circuit, and digital broadcast receiving method

When a branch instruction is decoded by the instruction decoders, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculatorand the lower 3 bits are sent to the lower PC calculator. The lower PC calculatoradds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PCand sends the result to the lower PCas the updated lower PC. The upper PC calculatoradds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC, and a carry that may be received from the lower PC calculator, and sends the result to the upper PCas the updated upper PC.

Processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor

A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1unit field in the parallel execution code, and the long instruction is assigned to the sunit field to the (s+k&#x2212;1)unit field in the same parallel execution code.

Instruction converting apparatus using parallel execution code

In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

Processor, compiler and compilation method

A compiling unit () generates indefinite branch information showing that an instruction set to be selected is indefinite, instead of generating a branch instruction. A linking unit () generates an appropriate direct addressing branch instruction by judging whether an instruction set used at a branch source and an instruction set used at a branch destination are the same. Also, one reference instruction set is determined. The compiling unit () adds a mode adjusting instruction that belongs to the reference instruction set and that is for causing a branch to an instruction placed at a branch destination and for selecting the instruction set that is originally to be selected. The mode adjusting instruction provides an alternative branch destination corresponding to an original branch destination, and the compiling unit () generates an indirect addressing branch instruction for causing a branch to the alternative branch destination and for selecting the reference instruction set.

Program conversion apparatus, program conversion method, and computer program for executing program conversion process

This invention makes debugging more efficient when an object program is intended for processing a loop made up of n groups of iteration-forming instructions. Instructions in the secondary assembler program each has a combination of a line number ';lx' and an iteration identifier ';ix' attached thereto. The line number &#x201c;;lx&#x201d; specifies a source code from which the instruction is generated, and the iteration identifier &#x201c;;ix&#x201d; specifies an iteration to which the instruction belongs. When the user sets a breakpoint at an instruction, displayed in the windows are (a) a source code for generating the instruction at the breakpoint and (b) another source code for generating another instruction that belongs to a different group of iteration-forming instructions than the breakpoint instruction.

Debugging aid parallel execution of a plurality of iterations with source lists display corresponding to each iteration

Disclosed is a compiler apparatus for generating an instruction code composed of instruction sets each including an instruction that designates an m-bit immediate value indicating a location of a data item in a memory area. The compiler apparatus sequentially selects, based on one data attribute, a data item from a group X composed of a plurality of data items; and judges, each time a data item is selected, whether the selected data item is allocatable to an n-byte memory area (n&#x2266;2). When the judgment is negative, the compiler apparatus specifies, based on a different data attribute, a data item out of all the selected data items and excludes the specified data item from the group X, and repeats the selection until all the data items remaining in the group X after excluding specified data items are judged to be allocatable to the memory area.

Compiler apparatus and method for determining locations for data in memory area

Growing community of inventors

Takarazuka, Japan

Shuichi Takayama