Nec Corporation

Shuichi Moriyama

Masataka Watanabe

Kazuhisa Iga

Masayuki Shimura

A CPU temperature control circuit is provided that can vary the clock frequency and the power source voltage of a central processing unit (CPU) while the CPU meets the operational specifications. The comparison circuit compares the temperature of the CPU measured by the CPU temperature sensor with temperature information previously stored in the ROM The CLK and power-source control circuit switches the clock frequency from a high frequency to a low frequency when the temperature of the CPU becomes high. Then, the CKL and power-source control circuit switches the power source voltage from a high voltage to a low voltage at the time the timer counts up. When the temperature of the CPU becomes low, the CLK and power-source control circuit switches the power source voltage from a low voltage to a high voltage. Then, the CLK and power-source control circuit switches the clock frequency from a low frequency to a high frequency at the time the timer counts up.

Temperature control circuit for central processing unit

A semiconductor integrated circuit comprises an internal logic circuit , a delay detecting circuit which monitors changes in delay length within the semiconductor integrated circuit , and a central control circuit which controls the quantity of processing per unit time length by the internal logic circuit on the basis of changes in delay length monitored by the delay detecting circuit

Semiconductor integrated circuit equipped with function for controlling the quantity of processing per unit time length by detecting internally arising delay

A cache flash controlling method for a cache memory system of the write back type wherein the time required for discrimination of a dirty line in a flash cycle is reduced and system performances are improved. In the cache controlling method, all lines having tag addresses of a cache memory are divided into a plurality of blocks, and for each of the blocks, a dirty detection bit indicating whether or not a dirty line is present in the block is prepared. For those of the blocks whose data line detection bit indicates presence of no dirty line, lines of the block are invalidated immediately without performing a discrimination operation of a dirty line.

Cache flash controlling method for cache memory system

A frequency dividing circuit/delay circuit is provided to generate a plurality of system clock signals according to the combination of frequency division and the delay based on a fast-speed basic clock signal to determine according to the address signal from a central processing unit (CPU) what the operating cycle of the slave is to select a system clock of optimum frequency or duty ratio for that slave. As a result, it becomes possible to shorten the time required for executing one cycle and, hence, to improve the performance of the whole personal computer system.

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Niigata, Japan

Shuichi Moriyama