Elpida Memory, Inc.

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Other

Micron Technology Incorporated

Hitachi Ulsi Engineering Corp.

Longitude Semiconductor S.a.r.l.

Shuichi Kubouchi

Hiroki Fujisawa

Koichiro Ninomiya

Jun Suzuki

Seiji Narui

Koji Kuroki

Kazuhiko Kajigaya

Hitoshi Tanaka

Hiroyuki Yamamoto

Yasuji Koshikawa

Hiromasa Noda

Shinichi Miyatake

Yoshiro Riho

Masatoshi Hasegawa

Masayuki Nakamura

Makoto Morino

Yasuhiro Matsumoto

Yousuke Tanaka

Kenji Mae

Daiki Nakashima

To provide an electrical fuse that is connected to a detection node via a selective transistor, a precharge transistor that precharges the detection node in a state where the selective transistor is off; a bias transistor that passes a bias current to the detection node in a state where the selective transistor is on and the precharge transistor is off, and a detection circuit that detects a potential of the detection node in a state where the bias current is flowing into the detection node, wherein the bias transistor reduces an amount of the bias current in a stepwise manner or a continuous manner.

Semiconductor device having electrical fuse and control method thereof

Disclosed herein is an apparatus that includes: a plurality of memory banks each including a plurality of memory cells; a plurality of redundant circuits each allocated to an associated one of the plurality of memory banks to replace a defective memory cell among the plurality of memory cells included in the associated memory bank; a plurality of roll call circuits allocated to an associated one of the plurality of memory banks to generate a roll call data when an address corresponding to the defective memory cell is supplied; and a plurality of data buses commonly allocated to the plurality of memory banks. The roll call circuits output the roll call data to the plurality of data buses in parallel.

Semiconductor device having roll call circuit

A bit memory circuit of an antifuse element set includes two antifuse elements of which logical states are changed from an insulation state to a conductive state when a program voltage is applied. 1-bit data is represented by the logical states of the two antifuse elements. The two antifuse elements are collectively controlled by one decoder circuit. When writing data, the decoder circuit simultaneously performs insulation-breakdown on the two antifuse elements by simultaneously connecting the two antifuse elements to program voltage lines, respectively.

Semiconductor device having nonvolatile memory elements

A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.

Semiconductor device having boosting circuit

To provided a relief-address generating circuit that generates relief address information based on plural data bits supplied in time sequence via a first terminal from outside and a programming circuit that writes into any one of fuse sets the relief address information generated by the relief-address generating circuit. With this configuration, repetition of a programming operation by the total number of the fuse sets at the maximum completes a series of write processing on relief address information. Therefore, it is possible to reduce the time required for a series of write processing on relief address information.

Semiconductor device, relief-address-information writing device, and relief-address-information writing method

A semiconductor memory device comprises a memory cell array having memory cells arranged at intersections of word lines and bit lines, a first sense amplifier connected to a bit line at a predetermined position of the bit lines, a second sense amplifier connected to a bit line adjacent to the bit line at the predetermined position, a supplying circuit for supplying a predetermined voltage to each bit line connected to the first or second sense amplifier, and a sense amplifier control circuit capable of controlling the first and second sense amplifiers independently. In the semiconductor memory device, the sense amplifier control circuit performs a control in which an operation of either of the first and second sense amplifiers is stopped, the predetermined voltage is supplied to the bit line connected to the stopped sense amplifier, and the other of the first and second sense amplifiers is operated.

Semiconductor memory device and test method thereof

There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.

Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address

A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.

Synchronous semiconductor memory device

In a semiconductor integrated circuit device, a write command decoder decodes a write command and outputs decode pulses. A command counter circuit counts the decode pulses as the number of commands. A latch circuit latches the write aDDRess in response to a count output from the command counter circuit. A latency counter circuit counts a latency in response to the decode pulses. The semiconductor integrated circuit device further includes a circuit for turning on a column selection control signal when the count value of the latency counter circuit exceeds a predetermined latency value and a circuit for outputting the aDDRess latched by the latch circuit as a column aDDRess in response to the column selection control signal being turned on. The semiconductor integrated circuit device performs a write operation to the column aDDRess in response to the column selection control signal being turned on.

Semiconductor integrated circuit device

A boosted potential generation circuit enables a high-speed operation and even miniaturization in a semiconductor memory even if external power supply voltage is reduced in the semiconductor memory. In the boosted potential generation circuit provided with a capacitor MOS transistor and a transfer MOS transistor and used for a DRAM including memory cells, a gate insulating film of the capacitor MOS transistor is thinner than that of the MOS transistor constituting the memory cell to realize a boosted potential generation circuit which has a small area and a large capacity. In this case, preferably, the gate insulating film of the transfer MOS transistor has a thickness which is not greater than that of the gate insulating film of the capacitor MOS transistor.

Boosted potential generation circuit and control method

Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word-lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines connected through bit lines and first selection circuits associated with such sense amplifier areas are provided. Second common input/output lines connected through the plurality of first common input/output lines and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.

Semiconductor memory device having a hierarchical I/O structure

Semiconductor memory device having a hierarchial I/O strucuture

In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.

Growing community of inventors

Tokyo, Japan

Shuichi Kubouchi