Matsushita Electric Industrial Co., Ltd.

Tokyo Shibaura Denki Kabushiki Kaisha

Matsushita Electric Ind., Ltd.

Shuichi Kameyama

Hiroshi Shimomura

Mizuki Segawa

Atsushi Hori

Kazuya Kikuchi

Hiroshi Iwai

Hiroyuki Sakai

Satoshi Shinozaki

Tadao Komeda

Kazuhiro Kobushi

Masaoki Kajiyama

Bunji Mizuno

Genshu Fuse

Shozo Okada

Kazuhiko Tsuji

Yoshitaka Sasaki

Norisato Shimizu

Koichi Kanzaki

Gen Sasaki

A semiconductor device having superior electrical characteristics is fabricated. 50 nm of the surface of a CZ (100) silicon substrate is oxidized to form an oxidized film. Afterwards a first ion implantation of boron ions is conducted to this silicon substrate amounting to 7.times.10.sup.13 cm.sup.-2 with acceleration energy of 1.5 MeV. Next, a first annealing in nitrogen ambient at 1050.degree. C. for 40 minutes is conducted. Through this ion implantation process a damaged layer and a dopant layer are formed within the silicon substrate. Boron ions are implanted as a second ion implantation, with a dosage of 7.times.10.sup.13 cm.sup.-2, followed by a second implanted annealing in nitrogen ambient at 1050.degree. C. for 40 minutes. Further, as a third ion implantation, boron ions are implanted with a dosage of 6.times.10.sup.13 cm.sup.-2 followed by a third annealing in nitrogen ambient at 1050.degree. C. for 40 minutes. In the dopant layer thus formed, through a plurality of repeated high energy ion implantation and subsequent annealing, in order to obtain the desired dopant concentration, density of secondary defect occurrences may be lowered.

Method for fabricating a semiconductor device by high energy ion

Insulating films formed on side walls of a gate electrode are removed for a self-alignment to selectively implant impurities only into end portions of a source region and a drain region. Therefore, p.sup.+ -type semiconductor regions are selectively formed only on sides near a channel region of the source and the drain regions. A punch through of the source or drain region is prevented by the p.sup.+ -type semiconductor regions controlling an inversion threshold voltage. Therefore, the impurity concentration of the p-type substrate can be settled low, and the semiconductor transistor device can be miniaturized without increasing a parasitic junction capacitance. Moreover, since the impurity concentration in the channel region is ununiform, a drivability of the transistor can be increased. As a result, a semiconductor transistor device with a high withstand voltage and a high drivability in which the inversion threshold voltage can be easily controlled, and a method for producing the same are provided.

Method for making semiconductor transistor device by implanting punch

A fabrication method for semiconductor devices connecting a multi-crystal semiconductor thin film and a semiconductor region including a high density of an impurity formed in a single crystal semiconductor substrate. After forming a N-type semiconductor region as the emitter by ion implanting, for instance, as into a P-type semiconductor region as the base, a polysilicon thin film 114 is deposited so as to be implanted with As ions and then heat treated. In this case, an amorphous portion of the N-type semiconductor region and an amorphous silicon thin film in contact therewith are transformed by solid phase epitaxial growth so as to form a single crystal semiconductor region, a single-crystalline silicon thin film, and a polysilicon thin film, thus forming a bipolar element having an emitter.

Fabrication method for semiconductor devices

An improved method for fabrication of a super-high density semiconductor device wherein ion implantation is used to eliminate defects or inhibit the occurrence of growth of defects in the semiconductor device. Ions of high concentration are implanted into a monocrystal semiconductor region in which principal elements such as bipolar element and MOS element are formed, by using a mask pattern covering the semiconductor region and at a largely inclined implantation angle equal to or of more than 20 degrees. This provides for formation of amorphous regions 170A, 170B extending sufficiently into areas beneath the ends of the mask. The amorphous regions are recrystallized by heat treatment, thereby inhibiting the growth of a corner defect known as 'voids 21' which has often occurred at edges of amorphous regions 170A, 170B in the conventional method. Thus, a device which is less liable to electrical leaks is provided.

Method for fabrication of semiconductor device utilizing ion

There is disclosed a method for manufacturing a bipolar semiconductor device in which emitter region and active base region are formed by implanting impurities of first and second conduction types in a first semiconductor region of the first conduction type to be a collector through a non-single crystalline semiconductor thin film, a second semiconductor thin film is formed on the first semiconductor thin film, and an impurity of the first conduction type is introduced in the second semiconductor thin film after patterning the first and second semiconductor thin film so as to form an emitter electrode.

Method for manufacturing bipolar semiconductor device

A method for fabricating a bipolar or field effect-type integrated circuit transistor is provided in which non-crystalline semiconductor films and semiconductive regions formed in a single crystal semiconductor substrate and containing high concentrations of impurities are efficiently connected with improved electric characteristics while suppressing the influence of an increase in connection resistance caused by growth of a natural oxide film. Moreover, when a first non-crystalline semiconductor film is removed from a dielectric oxide film serving as a field film and a second non-crystalline semiconductor film is formed as a ribbon-shaped pattern on the exposed field film, a resistor of high accuracy can be formed. An interconnection system having resistors of a high accuracy and a fine size is also disclosed.

Method for fabricating semiconductor devices

A method of fabricating a semiconductor device having gate-drain overlap MOSFETs in which side surfaces of upper portions of gate lines are anisotropically etched using a buffer film as an etch stop is disclosed. An insulating film as a gate insulator is formed on a semiconductor layer of a first conductivity type. A first conductive film is formed on the gate insulator. A buffer film having openings in gate line regions is formed on the first conductive film. A second conductive film is formed on the buffer film. The second conductive film is patterned into wiring shape to form upper portions of gate lines covering the openings of the buffer film. Ions of a second conductivity type are implanted into the semiconductor layer using the upper portions of the gate lines as an implant mask to form sources and drains in the semiconductor layer. Sidewall spacers are formed on the sides of the upper portions of the gate lines. The buffer film and the first conductive film are etched using the upper portions of the gate lines and the sidewall spacers as an etching mask to form under portions of the gate lines.

Method of fabricating a semiconductor device

A first semiconductor region is of a first conduction type and forms a transistor collector. A second semiconductor region is of a second conduction type and forms a transistor base. The second semiconductor region extends in the first semiconductor region. A third semiconductor region is of the first conduction type and forms a transistor emitter. The third semiconductor region extends in the second semiconductor region. A fourth semiconductor region is of the first conduction type and has a first portion and a second portion. The first portion extends in a part of the first semiconductor region below an edge of the third semiconductor region, and the second portion extends from the first semiconductor region into a part of the second semiconductor region outward of the edge of the third semiconductor region to limit a width of the transistor base.

Method of fabricating semiconductor device by forming doped regions that

A method for producing field-effect type semiconductor devices is disclosed which includes the steps of: forming a gate insulator film on a semiconductor substrate; forming a conductor film on the gate insulator film; and implanting impurity ions in the semiconductor substrate through the gate insulator film and the conductor film for the purpose of controlling a threshold voltage of the device, wherein the conductor film is employed as a gate electrode of the device. The method of this invention has the excellent advantages of readily controlling a threshold voltage of field-effect type semiconductor devices and of preventing the scatter of the threshold voltage values. An alternative embodiment employs formation of a second conductor film and implantation from an inclined direction.

Method for producing a field-effect type semiconductor device

A method for fabricating a bipolar or field effect-type integrated circuit transistor is provided in which non-cyrstalline semiconductor films and semiconductive regions formed in a single crystal semiconductor substrate and containing high concentrations of impurities are efficiently connected with improved electric characteristics while suppressing the influence of an increase in connection resistance caused by growth of a natural oxide film. Moreover, when a first non-crystalline semiconductor film is removed from a dielectric oxide film serving as a field film and a second non-crystalline semiconductor film is formed as a ribbon-shaped pattern on the exposed field film, a resistor of high accuracy can be formed. An interconnection system having resistors of a high accuracy and a fine size is also disclosed.

Method for fabricating bipolar semiconductor devices

Disclosed is a structure of a semiconductor integrated circuit such as bipolar transistor, along with the fabrication thereof, in which an active device region such an intrinsic base is formed from, at least, the bottom of the groove formed in a semiconductor substrate, and this active device region and a low resistance electrode take-out region such an extrinsic base formed around the groove are connected favorably with each other.

Semiconductor device and method for fabricating the same

A semiconductor device such as a Bi-CMOS having vertical or lateral bipolar transistors and MOS transistors is disclosed. The MOS transistors include a gate electrode made of a first conductive thin film, and sidewall spacers formed on the sides of the gate electrode and consisting of at least one deposition film. The vertical bipolar transistors include an emitter electrode made of a second conductive thin film, and an emitter diffusion window formed in the deposition film which is disposed under the emitter electrode. The lateral bipolar transistors include a base width defining region for defining the base width, and an insulation film formed between the base width defining region and the collector and emitter, and consisting of the deposition film.

Semiconductor device and method of manufacturing the same

In a semiconductor integrated circuit device using a field effect transistor, such as MOS, having the end part of the drain overlapped with the gate electrode, a novel gate-drain overlap structure of excellent performance and reliability is presented. A manufacturing method for this device is also presented.

Field effect semiconductor device and its manufacturing method

A method for fabricating a semiconductor device which is capable of enlarging diameter of crystal grain of a polycrystalline conductor by a heat treatment which is carried out after surface lower portion of the polycrystalline conductor is made amorphous with ion-implanting atoms in the polycrystalline conductor by predetermined accelerating energy to thereby improve the uniformity of size of crystal grain. By this method, the uniformity of impurity concentration distribution is improved in the polycrystalline conductor and also in the impurity diffusion area, and further, the uniformity of resistance of a resistor or conductor formed by the polycrystalline conductor is improved.

Method for fabricating a polycrystalline silicon resistor

A semiconductor device and a method of making a semiconductor device including a semiconductor substrate of p-type conductivity, a first semiconductor region of n.sup.+ -type conductivity selectively formed on the semiconductor substrate, a second semiconductor region of n-type conductivity formed insularly contacting on the first semiconductor region, a groove extending from a surface of the second semiconductor region spaced from the first semiconductor region to the vicinity of a surface of the first semiconductor region abutting the second semiconductor region, a conductive material charged into the groove, and a third semiconductor region of high impurity n-type conductivity disposed so as to connect a bottom of the groove with the surface of the first semiconductor region, whereby the conductive material in the groove and the third semiconductor region are used as low resistance current paths reaching from the surface of the second semiconductor region to the first semiconductor region.

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Itami, Japan

Shuichi Kameyama