Macronix International Co., Ltd.

Winbond Electronics Corporation

United Microelectronics Corp.

Shui-Chin Huang

Chien-Hung Chen

Tzyh-Cheang Lee

Chun-Jung Lin

Tso-Hung Fan

Chun-Yi Yang

Yen-Hung Yeh

Sung-Bin Lin

Nai-Chen Peng

Jen-Chuan Pan

Chuan Fu Wang

A low thermal budget fabrication method for a mask ROM is described. The method includes providing a substrate having a gate oxide layer thereon. A first conductive layer is formed on the gate oxide layer. A plurality of bit lines is formed in the substrate. A second conductive layer is then formed on the first conductive layer, followed by forming a plurality of ROM codes in the substrate.

Low thermal budget fabrication method for a mask read only memory device

The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first Pdoped drain region and a first Pdoped source region. The second PMOS transistor includes a gate and a second Pdoped source region. The first Pdoped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a Ndoped region. The floating gate overlaps with the N-well and extends to the Ndoped region. The overlapped region of the P-well and the Ndoped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

Single-poly EEPROM

A method for programming a P-channel EEPROM having an N-well, a floating gate, a control gate, a P-type source region and a P-type drain region is provided. In the method, the N-well is grounded, a first positive voltage is applied to the control gate, a second positive voltage or a programming current is applied to the P-type source region, and a negative voltage is applied to the P-type drain region.

Method for programming P-channel EEPROM

A method of programming and erasing an electrically erasable programmable read-only memory (EEPROM)device includes performing a band-to-band tunneling induced hot-electrons program and performing a Fowler-Nordheim tunneling erase. The EEPEOM device includes a P-type transistor, an N-type transistor, and a double gate P-type transistor. A source of the P-type transistor and the N-type transistor are respectively electrically connected to a program bit-line and an erase bit-line. A drain of the double gate P-type transistor is electrically connected to a drain of the P-type transistor and a drain of the N-type transistor.

Non-volatile memory and method of operation

A method of fabricating a memory device having a buried source/drain region is provided, in which a dielectric layer and a word-line is sequentially formed on the substrate, then a buried source/drain region is formed in the substrate. After that, a barrier layer is formed on the exposed surface of the word-line, then a metal layer is formed over the substrate. The metal layer is patterned to leave a portion covering the buried source/drain region beside the word-line and crossing over the word-line.

Memory device having buried source/drain region and fabrication thereof

Fabricating memory device having buried source/drain region and fabrication thereof

A vertical read-only memory (ROM) is provided, which includes a gate on a substrate, a source/drain at the bottom of a trench in the substrate, a polysilicon bit-line in the trench, and a dielectric layer separating the polysilicon bit-line and the side-walls of the trench. The polysilicon bit-line electrically connects with the source/drain. The substrate of the side-wall of the trench adjacent to the gate serves as a coding region.

Vertical read-only memory and fabrication thereof

The present invention relates to discloses a manufacturing method of a gate-split flash memory, which is suitable for a self-align contact process and fully-salicide-compatible process. The present invention masks the invalid peaks with a thick passivation layer to obtain the purpose of removing the invalid peaks in the manufacturing process of a gate-split flash memory. The present invention deposits a nitride spacer to define a pattern of a floating gate of the flash memory, so that a channel length of the floating gate can be finely defined. The present invention also utilizes a mask pattern to define the floating gate region of the flash memory, and the manufacturing process will be smooth and cheap.

Manufacturing method of a gate-split flash memory

A method of fabricating a mask ROM, in which conductive strips are formed with a cap layer on each of them, then a plurality of spacers are formed on the side-walls of the conductive strips, while the substrate under the spacers are used as the coding regions. The buried bit-lines are formed in the substrate between the spacers, then a two-step coding process is performed, wherein the coding regions at the first and the second side of the conductive strips are selectively doped by a first and a second tilt coding implantation with a first and a second coding mask. After the second mask layer and the cap layer are removed, a conductive layer is formed over the substrate, then the conductive layer and the conductive strips are patterned successively to form a plurality of word-lines and plural gates, respectively.

Method of fabricating a mask ROM with raised bit-line on each buried bit-line

A method of integrating salicide process and self-aligned contact process is performed on a semiconductor substrate on which a plurality of doped gate electrodes and source/drain regions are formed in both a memory device area and a peripheral area. An oxide layer is formed on the exposed surface, and then a plurality of spacers is formed on the sidewalls of the gate electrodes respectively. Sequentially, a barrier layer and a buffering layer are formed on the exposed surface. Next, the buffering layer and the barrier layer are removed from the top of the gate electrodes to expose the oxide layer. The exposed oxide layer and the underlying gate electrodes are then removed until the gate electrode reaches a predetermined height. The salicide process is performed to form a silicide on the exposed surface of the gate electrodes and simultaneously on the source/drain regions in the periphery area. Next, a gate cap layer is formed on the silicide overlying the gate electrodes. After forming an inter-layer dielectric on the exposed surface, the self-aligned contact process is performed to form a contact hole to expose the source/drain region positioned between adjacent gate electrodes in the memory device area.

Method of integrating a salicide process and a self-aligned contact process

A self-aligned contact process is provided on a semiconductor substrate having at least two gate structures and a plurality of lightly ion-doped regions on the semiconductor substrate. Each of the gate structures has a gate layer and a cap layer formed on the gate layer. A first sidewall spacer is formed on the sidewalls of the gate structure, and then a heavy ion-doped region is formed on the exposed lightly ion-doped region. Next, a first dielectric layer is formed to fill the gap between adjacent first sidewall spacers. Part of the first sidewall spacer and part of the first dielectric layer is removed to expose the cap layer. A second spacer is then formed on the exposed sidewall of the cap layer. Next, a second dielectric layer is formed to fill the gap between adjacent second sidewall spacers. Finally, the second dielectric layer and the first dielectric layer positioned adjacent gate structures are removed to expose the second ion-doped region so as to form a contact hole.

Self-aligned contact process using stacked spacers

A method for manufacturing the floating gate of a flash memory. First, a substrate is provided. A gate oxide layer, a polysilicon layer and a silicon nitride layer are sequentially formed over the substrate. Gate position is defined and then the silicon nitride layer above the gate position is removed. Th exposed polysilicon layer is oxidized to from a floating gate oxide layer. A buffer layer is formed over the silicon nitride layer and the floating gate oxide layer. A first spacer is formed on the sidewall of the buffer layer. Thereafter, a second spacer is formed. Using the second spacer as a mask, the exposed floating gate oxide layer is removed. The buffer layer, the first spacer and the second spacer above the polysilicon layer and the floating gate oxide layer are removed. Finally, the polysilicon layer not covered by the floating gate oxide layer is removed to form a complete floating gate of a flash memory.

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Tainan, Taiwan

Shui-Chin Huang