Marvell International Limited

Marvellworld Trade Ltd.

Shuhua Yu

Chuan-Cheng Cheng

Albert M Wu

Roawen Chen

Choy Hing Li

Sehat Sutardja

Weidan Li

Chung Chyung Han

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Power/ground layout for chips

A semiconductor wafer including an electrostatic discharge (ESD) protective device, and methods for fabricating the same. In one aspect, the method includes forming a first semiconductor device in a first semiconductor die region on the semiconductor wafer; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; and forming a protective device in a scribe line region between (i) the first semiconductor die region and (ii) the second semiconductor die region.

Integrated circuit devices with electrostatic discharge (ESD) protection in scribe line regions

Integrated circuit devices with ESD protection in scribe line, and methods for fabricating same

A semiconductor wafer with an electrostatic discharge (ESD) protective device is disclosed. The semiconductor wafer includes first and second adjacent semiconductor die regions, a protective device in a scribe line region between the first and second die regions, and at least one metal line on a surface of the first die region, wherein the metal line(s) is/are in electrical communication with the protective device.

A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

Methods of making and using fuse structures, and integrated circuits including the same

Fuse structures, methods of making and using the same, and integrated circuits including the same

A structure configured to disconnect circuit elements. The structure generally includes a dielectric layer over a light-absorbing structure, and a lens over the dielectric layer and the light-absorbing structure, configured to at least partially focus light onto the light-absorbing structure. The light-absorbing structure absorbs a first wavelength of light with a minimum threshold efficiency, the lens is substantially opaque to the first wavelength of light, and the dielectric layer is substantially transparent to the first wavelength of light. The structure advantageously provides improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

Growing community of inventors

Cupertino, CA, United States of America

Shuhua Yu