Hitachi, Ltd.

Shuhei Matsumoto

Hironori Inoue

Shintaro Wada

Norimitsu Hayakawa

Makiko Shinohara

Shoichi Takeuchi

Isao Watanabe

Hiroyuki Mitome

Akiko Mori

Kenichiro Yamato

A scheduling method whereby a virtualization unit, which has multiple nodes containing physical CPUs and physical memories, and which operates a virtual computer by generating logical partitions from the computer resources of the multiple nodes, allocates a physical CPU to the logical CPU. The multiple nodes are coupled via an interconnect, and the virtualization unit selects the physical CPU to be allocated to the logical CPU, and measures performance information related to the performance when the physical memory is accessed from the logical CPU. When the performance information satisfies a prescribed threshold value the physical CPU allocated to the logical CPU is selected from the same node as that of the previously allocated physical CPU, and when the performance information does not satisfy the prescribed threshold value the physical CPU allocated to the logical CPU is selected from a different node than the node of the previously allocated physical CPU.

Virtual computer system and scheduling method

A dispatcher stack is allocated to each of a plurality of processors sharing a run queue. Each processor, in process dispatch processing, saves in a switch-source process stack the context of a switch-source process (the process being run), saves in the dispatcher stack of each of the processors a dispatcher context, inserts the switch-source process into the run queue, removes a switch-destination process from the run queue, and, in addition, restores the context of the switch-destination process from the switch-destination process stack.

Computer with plurality of processors sharing process queue, and process dispatch processing method

In a computer system according to the background art, when a request to halt a virtual processor was detected, the virtual processor was blocked. In the blocking method, latency of virtual halt exit of the virtual processor was so long that a problem of performance was caused. A virtual machine monitor selects either of a busy wait method for making repeatedly examination until the virtual halt state exits while the virtual processor stays on the physical processor and a blocking method for stopping execution of the virtual processor and scheduling other virtual processors on the physical processor while yielding the operating physical processor and checking off scheduling of the virtual processor to the physical processor, based on a virtual processor halt duration predicted value of the virtual processor which is an average value of latest N virtual processor halt durations of the virtual processor.

Computer system

Computer including a plurality of physical CPUs, a plurality of virtual computers which execute predetermined processing and to which one of the plurality of physical CPUs is assigned, and a virtual computer control component able to cause the plurality of physical CPUs to execute overhead processing required by plurality of virtual computers. Virtual computer control component configured to: (A) upon causing the physical CPU, in which processing of the virtual computer is in a running state, to execute overhead processing, measure a run time used by the physical CPU to manage a cumulative run time, for each of the physical CPUs; and (B) upon causing the overhead processing to be executed subsequent to the (A), select a physical CPU in which the cumulative run time is smallest as the physical CPU to execute the overhead processing.

Computer, virtualization mechanism, and scheduling method

The method of calculating the processor utilization for each of logical processors in a computer, including the steps of: dividing the computation interval in which the processor utilization by each logical processor is to be calculated into a single task mode (ST) execution interval and a multitask mode (MT) execution interval, appropriately calculating them based on the before-and-after relation between two times; and adding the MT execution interval multiplied by a predetermined MT mode processor resource assignment ratio to the ST mode execution interval to obtain the processor utilization for the calculation-targeted logical processor in the computation interval.

Method of calculating processor utilization rate in SMT processor

A hypervisor calculates the total number of processor cycles (the number of processor cycles of one or more physical processors) in a first length of time based on the sum of the operating frequencies of the respective physical processors and the first length of time for each first length of time (for example, a scheduling initialization cycle T, which will be explained further below). The hypervisor calculates for each virtual computer the number of possessing cycles, which is a value obtained by the total number of processor cycles being distributed in proportion to the service ratios of multiple virtual computers. In virtual processor scheduling, the hypervisor runs a virtual processor inside a virtual computer on any physical processor based on the number of hold cycles of each virtual computer.

Computer system and method of scheduling a virtual processor to run on physical processors based on the number of possessing cycles of each virtual computer

When the number of logical CPUs increases as the number of LPARs increases, a physical CPU amount which a hypervisor uses will increase and thus the physical CPU resource cannot be effectively utilized. Grouping of LPARs and physical CPUs is performed and a logical CPU to which a physical CPU is allocated is selected from logical CPUs of an LPAR within a group.

Virtual computer and CPU allocation method

Computer system, virtual machine monitor and scheduling method for virtual machine monitor

In scheduling shared processing that has a higher priority than LPAR processing, giving precedence to physical CPUs running idle LPARs prevents prolonged hold-up of LPAR processing. In a system is comprised of multiple physical CPUs, multiple LPARs to which these physical CPUs are allocated and which execute programs under their guest OSes, and a management program managing these LPARs, a few additional units are introduced: a guest OS monitoring unit that can grasp the states of guest OSes running on these LPARs and a dispatcher unit that allocates one of these physical CPUs to shared processing requested by the management program, which has a higher priority than LPAR processing. When a request for shared processing arises, the dispatcher unit interrogates the guest OS monitoring unit and, based on the information obtained from it, gives priority of allocation to the physical CPU processing an idle LPAR.

Attempts are made to reduce the system overhead generated at the time of context save/restore processing to perform process switching in a virtual machine system. In a CPU occupancy mode that a physical CPU is exclusively allocated to virtual machines, a logical CPU process running on the physical CPU is static, so that it is not necessary to save/restore the context every time the processes are switched. When a switching source process is a logical CPU process in a CPU occupancy mode, a context save is temporarily suspended. When switching to the same logical CPU process is made again continuously, save/restore is skipped. When the logical CPU process of a VMM control VM runs in that period, the logical CPU process whose save is delayed is recorded and saved late.

Virtual machine system, hypervisor in virtual machine system, and scheduling method in virtual machine system

A virtual machine control method and a virtual machine system are disclosed. In the case where a guest program can be operated in a plurality of address translation modes and the same guest virtual address is translated into different host real addresses in each address translation mode, the illegal access to a host real address by illegal address translation by double registration in the same page table is avoided, and the address translation mechanism is efficiently operated. A plurality of host page tables are prepared in the main storage, and one of the host page tables is selected with the change in address translation mode of the guest program. The bottom address of the selected host page table is set in the host page table register thereby to switch the host page table.

Growing community of inventors

Yokohama, Japan

Shuhei Matsumoto