Gpower Semiconductor, Inc.

Dynax Semiconductor, Inc.

Shufeng Zhao

Disclosed are a semiconductor device and a preparation method thereof. The semiconductor device includes a substrate, a multilayer semiconductor layer, a dielectric layer, a source and a drain. A gate trench is formed in the multilayer semiconductor layer and the dielectric layer. A gate is formed in the gate trench, and the gate trench includes a first sub-portion of the gate trench formed in the multilayer semiconductor layer and a second sub-portion of the gate trench penetrating the dielectric layer. The second sub-portion of the gate trench includes a second opening located on the surface of the dielectric layer close to the substrate and a third opening on the surface of the dielectric layer away from the substrate. The vertical projection of the third opening on the substrate covers the vertical projection of the second opening on the substrate.

Semiconductor device and preparation method thereof

A semiconductor packaging structure for packaging a semiconductor chip is disclosed, the semiconductor chip comprises at least two electrodes, each of the at least two electrodes comprises at least one electrode opening, and the packaging structure comprises: a packaging chassis, provided with at least two pin electrodes respectively corresponding to the at least two electrodes; and at least two extended electrodes, each of the at least two extended electrodes being electrically connected to one of the at least two pin electrodes, and comprising at least one conductive pillar for inserting into the at least one electrode opening formed on one of the at least two electrodes.

Semiconductor packaging structure and semiconductor device

A semiconductor package structure comprises: a high-voltage depletion type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a low-voltage enhancement type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a shell comprising a cavity for receiving the high-voltage depletion type semiconductor transistor and the low-voltage enhancement type semiconductor transistor, and a high-voltage terminal, a first low-voltage terminal and a second low-voltage terminal; and cascade circuits comprising a supporting sheet having a conductive surface. The source electrode of the high-voltage depletion type transistor and the drain electrode of the low-voltage enhancement type semiconductor transistor are fixed to the conductive surface of the supporting sheet and electrically connected to each other through the conductive surface of the supporting sheet. A side of the supporting sheet away from the conductive surface is fixed to the cavity of the shell.

Growing community of inventors

Suzhou, China

Shufeng Zhao