Linfinity Microelectronics

Sandisk Technologies Inc.

Samsung Semiconductor Inc.

Integrated Power Technologies, Ltd.

Syncira Corporation

Shufan Chan

Ekram Bhuiyan

Daniel Shum

A signal generating circuit and method are disclosed that do not require a phase-locked-loop and a low frequency temperature-stable oscillator. The method may include generating an oscillating output signal responsive to a feedback signal, where the feedback signal controls a frequency of the oscillating output signal, generating a current output signal having a magnitude corresponding to the frequency of the oscillating output signal, and then comparing the current output signal to a reference signal to generate the feedback signal. The signal generating circuit may include an oscillator circuit responsive to a feedback signal and a frequency-to-current conversion circuit configured to generate a frequency dependent current signal that is compared to a reference current to generate an output signal corresponding to the frequency of the oscillating output signal. A feedback conversion circuit compares the output signal with a reference signal to generate the feedback signal to the oscillator circuit.

Temperature-stable oscillator circuit having frequency-to-current feedback

In embodiment of the invention, a method of synthesizing a layout of an integrated circuit chip including analog circuitry is disclosed. The method includes receiving a circuit netlist of an integrated circuit chip including analog circuitry; representing and manipulating a hierarchical analog circuit layout including device placement and net routing in response to the circuit netlist, the hierarchical analog circuit layout including a plurality of levels of layout hierarchy; and passing layout information from one level of the layout hierarchy to an adjacent level of the layout hierarchy to synthesize the layout of the integrated circuit chip.

Hierarchical analog layout synthesis and optimization for integrated circuits

A dead time regulating apparatus is used in a switch mode power system. The apparatus, comprises a power MOSFET circuit with PMOS and NMOS devices. Driving means is connected for driving and for turning-on a delay in the MOSFETs. A time delay detecting means is connected for detecting dead time during MOSFET turn on and a pulse width comparing means is connected for receiving dead time signals and synchronous pulses for generating control signals. The control signals are directed to the driver means respectively for adjusting turn-on delays. The method of the invention provides precise dead time control in the MOSFET devices. The circuit drives the two MOSFET devices such that there is precise control of the dead time during on-off switching.

Power MOSFET switching dead time control method and apparatus

An improved low voltage dropout regulation circuit is provided. The internal compensating capacitance coupled to the regulated output port is coupled to a virtual ground and the virtual ground is current buffered for coupling to the control electrode of the path element. For additional frequency compensation, particularly when the path element has a large capacitance, an additional internal compensating capacitance is coupled between the input of the dropout circuit and an output of a transconductance amplifier, which is responsive to the voltage at the regulated output port.

Low voltage dropout circuit with compensating capacitance circuitry

An improved low voltage dropout regulation circuit is provided. The internal compensating capacitance coupled to the regulated output port is coupled to a virtual ground and the virtual ground is current buffered for coupling to the control electrode of the path element.

An improved output stage for a CMOS circuit is disclosed. In particular, the circuit drives both output transistors of a push-pull output in class AB operation for efficient power usage with low noise and distortion with a minimal number of components.

Low distortion efficient large swing CMOS amplifier output

A circuit for converting an input signal with an arbitrary duty cycle to an output signal with a 50 percent duty cycle. A bandpass filter removes unwanted DC and high frequency components from the input signal. A comparator compares the filtered signal to a reference voltage and provides very high gain amplification to produce an output signal having a 50 percent duty cycle. In one embodiment, two bandpass filters are used to condition the signal prior to providing it to the comparator. Each bandpass stage is comprised of a low pass filter followed by a high pass filter.

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Anaheim Hills, CA, United States of America

Shufan Chan